This work presents a parallel electrical interconnection process by means of flip-chip, selective electroplating and bonding. The electrical interconnection lines are built on a glass substrate made of 500/2000 Å of Cr/Au with 3150 lm in length and 10 lm in width. Two silicon chips are processed as the device chips to be electrically interconnected. It has been demonstrated that 98 out of 102 i...

We summarize two approaches to integrated multiscale process simulation (IMPS), particularly relevant to integrated circuit (IC) fabrication, in which models for equipment (m) and feature (lm) scales are solved simultaneously. The first approach uses regular grids, and is applied to low-pressure chemical vapor deposition (LPCVD) of silicon dioxide from tetraethoxysilane (TEOS). The second appro...

Thirty-five zeranol-implanted (I) and nonimplanted (NI) ram and wether lambs representing four treatments (implanted rams [IR], nonimplanted rams [NIR], implanted wethers [IW], and nonimplanted wethers [NIW]) were evaluated for meat palatability and muscle collagen characteristics. Rib (longissimus muscle, LM) chops from I lambs were juicier (P less than .05) than rib chops from NI lambs. Chops...

0026-2714/$ see front matter 2011 Elsevier Ltd. A doi:10.1016/j.microrel.2011.12.020 ⇑ Corresponding author. Tel.: +82 42 350 3375; fax E-mail address: [email protected] (K.-W. Paik). Various fine pitch chip-on-film (COF) packages assembled by (1) anisotropic conductive film (ACF), (2) nonconductive film (NCF), and (3) AuSn metallurgical bonding methods using fine pitch flexible printed circui...

In this work, the effect of copper through-silicon via (TSV) interconnect diameter on stress buildup in Cu TSVs was experimentally determined using a synchrotron-based X-ray microdiffraction technique. A single chip with different Cu TSV diameters (3, 5, and 8 lm), all having the same depth and processing conditions was studied. Prior to the measurements, the chip was annealed at 420 C (30 min)...