This tutorial surveys the state of the art in high-level synthesis of digital drcuits. It will be published in Advances in Computers, Volume 35, edited by M. Yovits.

The scheduling problem — one of the central tasks in high-level synthesis — is the problem of determining the order in which the operations in the behavioral description will execute. This tutorial introduces the scheduling problem, and describes four scheduling algorithms commonly used today to solve those problems.

In a high level synthesis environment there is a strong need for flexible module generators. For the generation of regular structures efficient dedicated module generators can be built. This paper describes the structure of a ’block– multiplier’, which features a wide range of area–time tradeoffs maintaining efficiency. The structure makes it possible to implement a fully serial or a fully para...

| This paper describes a novel approach to high-level synthesis of arbitrarily complex pipelined circuits, including pipelined circuits with feedback, and the synthesis algorithm that makes the approach viable in practice. Our approach provides a high-level, modular speciication language with an eecient implementation. In our system, the designer speciies the circuit as a set of independent mod...

T/ie paper describes objcctives of high-level synthesis. It concentrates on operation scheduling strategies and thc interaction with the resource allocation. Some transformational and iterative/constructive scheduling algorithms are described. Moreover, a new scheduling/alhcation approach is prcsented and compared with other known algorithms. Finally, some open problems of the high-levcl synthe...

In this paper, we present a first approach for array-level energy estimation during high-level synthesis when mapping piecewise regular algorithms onto massively parallel full size processor arrays. Innately, piecewise regular algorithms have some power consumption friendly properties, e.g., they may be mapped onto processor arrays with only local interconnect and memory. In addition to these p...

A known problem in the area of hardware/software codesign is the selection of the proper interface between the different parts of the design. This paper presents a technique which eases the selection by combining different synthesis techniques together with rapid prototyping. Application field of the technique is the design of communication systems where C and VHDL are generated from a specific...

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