In this paper, optimal 2-D Systolic Arrays for orthogonal matrix multiplication, as much as the corresponding hardware implementation is investigated. The selected platform is a FPGA (Field Programmable Gate Array) device since, in systolic computing, FPGAs can be used as dedicated computers in order to perform certain computations at very high frequencies. The description language used as an e...

This paper presents a high-level hardware design environment called Pollux. A design description is written with the Lustre data-ow language, and used by the diierent Pollux tools to produce the corresponding synchronous circuit or, for example, a simulation program, that can be compiled and executed on a sequential machine. Lustre has been chosen because it is well-suited to hardware descripti...

In efforts to overcome the complexity of the syntax and the lack of formal semantics in conventional hardware description languages (most notably Verilog and VHDL), a number of approaches based on functional languages have been proposed. The merits of functional languages as hardware description languages can be attributed to the fact that basic building blocks for hardware circuits are equival...

Knowledge of hardware description languages is an important element in the educational background of both undergraduate and graduate electrical and computer engineering students. However, the manner in which they are exposed to hardware description languages should differ because of the different level of maturity of the student populations. Graduate students are mature intellectually and thus ...

General purpose functional languages such as Haskell, have been widely used as host languages for the embedding of domain specific languages. In particular, various hardware description languages have been successfully embedded in Haskell and other functional languages. More recently, meta-programming languages have also started being used for the embedding of such languages, where the meta-lan...

Pipelined algorithms implemented in field programmable gate arrays are being extensively used for hardware triggers in the modern experimental high energy physics field and the complexity of such algorithms are increases rapidly. For development of such hardware triggers, algorithms are developed in $\texttt{C++}$, ported to hardware description language for synthesizing firmware, and then port...

We propose in this paper an algebraic approach to hardware/software partitioning in Verilog Hardware Description Language (HDL). We explore a collection of algebraic laws for Verilog programs, from which we design a set of syntax-based algebraic rules to conduct hardware/software partitioning. The co-specification language and the target hardware and software description languages are specific ...

A foggy environment may cause digitally captured images to appear blurry, dim, or low in contrast. This will impact computer vision systems that rely on image information. With the need for real-time information, such as a plate number recognition system, simple yet effective enhancement algorithm using hardware implementation is very much needed fulfil need. To improve suffer from exposure and...

This paper describes our experiences with the hardware description language Verilog during the development of the Xputer prototype. At first it introduces the novel non-von Neumann architecture of the Xputer, its need for efficient address generation and the basic structure of the Generic Address Generator. After a short introduction to Verilog, we discuss the problems with this hardware descri...