In this paper, we have proposed a new approach for optical failure analysis which employs a CMOS photon-emitting circuitry, consisting of a flipflop based on a sense amplifier and a photon-emitting device. This method can be used even with deepsubmicron processes where conventional optical failure analyses are difficult to use due to the low sensitivity in the near infrared (NIR) region of the ...

In this paper, a high performance pulse Triggered flipflop design is presented. The proposed design reduces the number of transistors stacked in the discharging path and also reduces the overall switching delay. This enhanced pulse triggered low-power flip flop (EPTLFF) avoids unnecessary internal node transitions to improve the power consumption as compared to previously designed circuits. A 4...

This paper proposes a self-checking Cell Logic Block (CLB) that can be used as building block for on-line testable FPGAs. The proposed cell consists, basically, of a 4 input Look-UpTable @UT) and a D FlipFlop. The CLB is designed using pass-transistor-based multiplerers, either to select the output of the Cinput Lm, or to select signals from other CLBs. The proposed CLB architecture is characte...

The logic construction of a double-edge-triggered (DET) flip-flop, which can receive input signal at two levels of the clock, is analyzed and a new circuit design of CMOS DET flip-flop is proposed. Simulation using SPICE and a 1μ technology shows that this DET flip-flop has ideal logic functionality, a simpler structure, lower delay time, and higher maximum data rate compared to other existing ...

In current scenario highresolutionADC architecture based on a resetting modulator required high gain operational Transcoductace Amplifier (OTA)and quanitizerin low-voltage nanometer-scale CMOSprocesses because of good speed and calibration-free response are becoming more popular in communication system. Proposed work achieves such high resolution, despite poor component matching using Folded ca...

This paper explains the design of two stage operational amplifier, single bit comparator and D flipflop best suited for the fifth order continuous-time sigma-delta modulator. A fifth order continuous time sigma delta modulator is chosen for 40MHz Signal Bandwidth with an nyquist frequency of 150MHz. Two stage opamp is used to provide the high gain to the modulator. A single quantizer is used to...

A reduced clock-swing flip-flop (RCSFF) is proposed, which is composed of a reduced swing clock driver and a special flip-flop which embodies the leak current cutoff mechanism. The RCSFF can reduce the clock system power of a VLSI down to one-third compared to the conventional flip-flop. This power improvement is achieved through the reduced clock swing down to 1 V. The area and the delay of th...