New designs for Hybrid latch flip-flip (HLFF) and implicit-pulsed data-close-to-output (ip-DCO) flipflop circuits are proposed to improve the redundant switching activity, speed and power as these flip-flop circuits are basic building blocks of many timing elements. This paper evaluates and compares the performance of various flip-flop circuits which can reduce the effect of redundant switching...

Flip and flop splice variants of AMPA receptor subunits are expressed in distinct but partly overlapping patterns and impart different desensitization kinetics to cognate receptor channels. In the absence of specific antibodies, isoform-specific differences in trafficking or localization of native flip and flop subunits remain uncharacterized. We report that in several transfected cell lines, t...

A novel Single Event Upset (SEU) tolerant flip-flop design is proposed, which is well suited for very-low power electronics that operate in subthreshold (<Vt ≈ 500 mV). The proposed flip-flop along with a traditional (unprotected) flip-flop, a Sense-Amplifier-based Rad-hard Flip-Flop (RSAFF) and a Dual Interlocked storage Cell (DICE) flip-flop were all fabricated in MIT Lincoln Lab’s XLP 0.15 μ...

− This paper describes novel low-power high-speed flip-flop called dual edge-triggered NAND keeper flip-flop (DETNKFF). The flip-flop achieves substantial power reduction by incorporating dual edge-triggered operation and by eliminating redundant transitions. It also minimizes the data-tooutput latency by reducing the height of transistor stack on the critical path. Moreover, DETNKFF allows neg...

In this paper, a low voltage dual-pulse-clock double edge triggered D'flip-flop (DPDET) is proposed. The DPDET flip-flop uses a split output latch clocked by a short pulse train. Compared to the previously reported double edge triggered flip-flops, the DPDET flip-flop uses only six transistors with two transistors being clocked, operating correctly under low supply voltage. The total transistor...

Efficient power management in wireless sensor network is a critical issue as the sensor nodes are low powered devices. In a sensor node, flip flop consumes large amount of power as they make maximum number of internal transitions. Reduction in the power consumed by flip-flops shows a deep impact on the total power consumed. Hence, designing low power flip flop cells are highly important for enh...

In this paper we present an ultra low-voltage and high speed D flip-flop. The flip-flop has an increased current level compared to standard CMOS circuits operating at low supply voltages. The increased current level is obtained by using a synchronized capacitive coupling to a semi floating-gate. The delay of the static differential flip-flop presented is less than 12% compared to conventional d...

In this paper, a novel low power pulsed flip-flop (PFF) using self-controllable pass transistor logic is presented. The pulse generation logic comprising of two transistor AND gate is used in the critical path of the design for improved speed and reduced complexity. In the D to Q path inverter is removed and the transistor is replaced with pass transistor logic. The pass transistor is driven by...

A new flip-flop design using a double-pulsed static latch is presented. The flip-flop has only a single stage of logic in the critical path and as a result is up to three times faster than the fastest previously known flip-flops, while consuming approximately the same energy as the lowestpower flip-flops. The flip-flop has asymmetric timing properties which make it a good match to skewed logic ...

The jitter, obtained by SFEMG recordings, mainly reflects the neuromuscular transmission time variability and is usually Gaussian distributed. Here is reported the bimodal distribution of the interpotential intervals, the flip-flop phenomenon. Long flip-flop in cases of reinnervation may indicate alternatively continuous and saltatory nerve conduction. Short flip-flop in normal subjects may be ...