In this paper, a Novel Hybrid ADC consisting of two-step quantizer which has Flash ADC and SAR ADC along with Resistor String DAC is designed and implemented. This Hybrid ADC improves the speed by employing Flash ADC and resolution and power reduction can be achieved by utilizing SAR ADC. The Hybrid architecture carrying 12 bits as resolution, input frequency as 100MHz and sampling frequency is...

This work describes a 12-bit 100 MS/s 0.13 μm CMOS three-stage pipeline ADC with various circuit design techniques to reduce power and die area. Digitally controlled timing delay and gatebootstrapping circuits improve the linearity and sampling time mismatch of the SHA-free input network composed of an MDAC and a FLASH ADC. A single two-stage switched op-amp is shared between adjacent MDACs wit...

. A 6-bit 1.2 Gs/s non-calibrated flash ADC in a standard 45nm CMOS process, that achieves 0.45pJ/conv-step at full Nyquist bandwidth, is presented. Power efficient operation is achieved by a full optimization of amplifier blocks, and by innovations in the comparator and encoding stage. The performance of a non-calibrated flash ADC is directly related to device properties; a scaling analysis of...

With the advancement of technology, data converters are widely used in modern communication and digital signal processing. ADCs are basic building blocks in many applications including storage systems, optical communication, radar communication, instrumentation and high-speed serial data links[1]. Different categories of ADC architectures are available based on their speed, resolution and power...

The analog to digital converters is the key components in modern electronic systems. As the digital signal processing industry grows the ADC design becomes more and more challenging for researchers. In these days an ADC becomes a part of the system on chip instead of standalone circuit for data converters. This increases the requirements on ADC design concerning for example speed, power, area, ...

In the present paper, a 4-bit flash analog to digital converter for low power SoC application is presented. CMOS inverter has been used as a comparator and by adjusting the ratio of channel width and length, the switching threshold of the CMOS inverter is varied to detect the input analog signal. The simulation results show that this proposed 4-bit flash ADC consumes about 12.4 mW at 200M sampl...

This paper concerns the design of Flash type of Analog to Digital Converter (ADC) which is more likely to be used for high quality audio and video signals. It uses resistor ladder logic, comparator and encoder to convert the continuous input signal into binary form. Comparator, encoder circuits are designed using CMOS technology and its output response is obtained to meet the requirements. Comp...

In February 2007 the MAGIC Air Cherenkov Telescope for gamma-ray astronomy was fully upgraded with an ultra fast 2 GSamples/s digitization system. Since the Cherenkov light flashes are very short, a fast readout can minimize the influence of the background from the light of the night sky. Also, the time structure of the event is an additional parameter to reduce the background from unwanted had...

In this paper, design of low power, 9-bit pipeline ADC architecture is introduced .A pipeline ADC architecture has a 3-stage pipeline ADC with 3-bit flash ADC followed by a 3-bit DAC at each stage. A novel approach to design a 3-bit ADC is implemented; this design offers less number of comparator and low power consumption with less circuit complexity based on this idea a 9-bit ADC is simulated ...

VERITAS employs a multi-stage data acquisition chain that extends from the VME readout of custom 500 MS/s flash ADC electronics to the construction of telescope events and ultimately the compilation of information from each telescope into array level data. These systems provide access to the programming of the channel level triggers and the FADCs. They also ensure the proper synchronization of ...