What is the minimum number of extra qubits needed to perform a large fault-tolerant quantum circuit? Working in a common model of fault-tolerance, I show that in the asymptotic limit of large circuits, the ratio of physical qubits to logical qubits can be a constant. The construction makes use of quantum low-density parity check codes, and the asymptotic overhead of the protocol is equal to tha...

Fault tolerant design is a technique emerging in Integrated Circuits (IC’s) to deal with the increasing error susceptibility (Soft Errors, or Single Event Upsets, SEU) caused by e.g. alpha particles. A side effect of these methods is that they also compensate for manufacturing defects (the Hard Errors). Currently, yield engineers focus on perfecting the manufacturing process and designers spend...

Transient faults in VLSI circuits could lead to disastrous consequences. With technology scaling, circuits are becoming increasingly vulnerable to transient faults. This papers presents an accurate and efficient method to estimate fault-sensitivity of VLSI circuits. Using a binary counter and an RC5 encryption implementation as examples, this paper shows that by performing a limited amount of r...

Genetic Algorithm based automatic evolution of fault tolerant digital circuits has been examined at three different levels. At the first level, multiple working designs are automatically generated, offline, without additional human design effort and each is documented with the unused resources information. This information is used for fault tolerance. Depending on the number of versions generat...

Most work in quantum circuit optimization has been performed in isolation from the results of quantum fault-tolerance. Here we present a polynomial-time algorithm for optimizing quantum circuits that takes the actual implementation of fault-tolerant logical gates into consideration. Our algorithm re-synthesizes quantum circuits composed of Clifford group and T gates, the latter being typically ...

Historically, there has been a lack of CAD tools for the design of on-line testable circuits. As a consequence, the design of on-line testable circuits is currently being made manually to a large extent. In this paper we propose a new tool for the automatic insertion of faulttolerant structures in an HDL synthesizable description of the design. With this tool, a fault-tolerant version of the de...

A clustered neural network, in which neuronal information is represented by a cluster (population of neurons), rather than a single neuron, is a possible solution to construct fault-tolerant singleelectron circuits. We designed single-electron circuits based on a clustered neural network that performs differential enhancement where differences between the cluster’s outputs receiving various mag...

Implementing a unitary operation using a universal gate set is a fundamental problem in quantum computing. The problem naturally arises when we want to implement some quantum algorithm on a fault tolerant quantum computer. Most fault tolerant protocols allow one to implement only Clifford circuits (those generated by CNOT, Hadamard and Phase gates). To achieve universal quantum computation one ...

Fault Tolerance (F-T) is an important issue in electronic devices. Detecting and even correcting internal faults during normal operation makes possible the usage of these circuits in critical applications. F-T has been taken into account for many years during design process of these applications, but it has not obtained any profit of latest advances in automatic CAD tools that optimise the desi...

We study the problem of constructing a sorting circuit, network, or PRAM algorithm that is tolerant to faults. For the most part, we focus on fault patterns that are random, e.g., where the result of each comparison is independently faulty with probability upperbounded by some constant. All previous fault-tolerant sorting circuits, networks, and parallel algorithms require R(log2 n) depth (time...