This paper presents a detailed study of the nonuniform bipolar conduction phenomenon under electrostatic discharge (ESD) events in single-finger NMOS transistors and analyzes its implications for the design of ESD protection for deep-submicron CMOS technologies. It is shown that the uniformity of the bipolar current distribution under ESD conditions is severely degraded depending on device fing...

A new power-rail ESD clamp circuit designed with PMOS as main ESD clamp device has been proposed and verified in a 65nm 1.2V CMOS process. The new proposed design with adjustable holding voltage controlled by the ESD detection circuit has better immunity against mis-trigger or transient-induced latch-on event. The layout area and the standby leakage current of this new proposed design are much ...

This paper proposed a silicon controller rectifier (SCR) based ESD protection device to protect low voltage ESD for integrated circuit. The proposed ESD protection device has low trigger voltage and high holding voltage compared with conventional SCR-based ESD protection devices. The proposed ESD protection circuit is verified and compared by TCAD simulation. This paper verified effective low v...

This paper reports a design of a bonding pad oriented square-shape ESD (electrostatic discharge) protection structure. The novel ESD protection structure provides adequate protection for IC chips against ESD pulses in all directions. The structure features deep snapback symmetric characteristics, low discharging impedance, low holding voltage, and flexible triggering voltage. It passed 14KV HBM...

Objective: Randomised controlled trials have shown the benefits of Early Supported Discharge (ESD) of stroke survivors. Our aim was to evaluate whether ESD is still beneficial when operating in the complex context of frontline healthcare provision. Design: We conducted a cohort study with quasi experimental design. A total of 293 stroke survivors (transfer independently or with assistance of on...

CDM ESD event has become the main ESD reliability concern for integrated-circuits products using nanoscale CMOS technology. A novel CDM ESD protection design, using self-biased current trigger (SBCT) and source pumping, has been proposed and successfully verified in 0.13-lm CMOS technology to achieve 1-kV CDM ESD robustness. 2007 Elsevier Ltd. All rights reserved.

Electrostatic discharge (ESD) protection design for mixed-voltage I/O interfaces has been one of the key challenges of system-on-achip (SOC) implementation in nanoscale CMOS processes. The on-chip ESD protection circuit for mixed-voltage I/O interfaces should meet the gate-oxide reliability constraints and prevent the undesired leakage current paths. This paper presents an overview on the desig...

Recently, a new approach has been introduced that leverages and over-provisions energy storage devices (ESDs) in data centers for performing power capping and facilitating capex/opex reductions, without performance overhead. To fully realize the potential benefits of the hierarchical ESD structure, we propose a comprehensive design, control, and provisioning framework including (i) designing po...

Education for Sustainable Development (ESD) has emerged in response to the negative consequences of economic and industrial processes. These issues are highly complex and their mitigation suggests social and economic transformation underpinned by a paradigm shift in favour of sustainability. Higher Education (HE) plays a crucial role in ESD; however there is little research which has investigat...