The authors report a 0.7V Manchester carry look-ahead circuit using partially depleted (PD) SOI CMOS dynamic threshold (DTMOS) techniques for low-voltage CMOS VLSI systems. Using an asymmetrical dynamic threshold pass-transistor technique with the PD-SOI DTMOS dynamic logic circuit, this 0.7V PD-SOI DTMOS Manchester carry look-ahead circuit has an improvement of 30% in propagation delay time co...

− Noise in deep submicron technology combined with the move towards dynamic circuit techniques for higher performance have raised concerns about reliability and energyefficiency of VLSI systems in the deep submicron era. To address this problem, a new noise-tolerant dynamic circuit technique is presented. In addition, the average noise threshold energy (ANTE) and the energy normalized ANTE metr...

In this paper, footless domino logic buffer circuit is proposed. It minimizes redundant switching at the dynamic and the output nodes. This circuit passes propagation of precharge pulse to the dynamic node and avoids precharge pulse to the output node which saves power consumption. Simulation is done using 0. 18μm CMOS technology. We have calculated the power consumption, delay and power delay ...

This paper presents two new results for multiplevalued switch-level algebra (MSA for short). The first is the use of MSA to descaibe the bidirectional switching function of MOS transistors and, thereby, to analyze binary MOS bridge Circuits. The second is the use of MSA to describe the function of capacitors and, thereby, to analyze binary MOS dynamic circuits. The results presented in this pap...

This paper presents the comparison between CMOS dynamic latch comparators. The circuit has been simulated using SPICE tool with 0.35μm technology, supply voltage of 3 V and 3.3 V respectively. The circuits studied and simulated in this paper are Preamplifier dynamic latch circuit that consists of a preamplifier followed by a double regenerative dynamic latch and the Buffered dynamic latch circu...

Historically, dynamic CMOS was used sparsely by using the property of dynamic nodes. If the transistor leakage current is relatively low so that a circuit node can retain its charge for a relatively long time, the presence and absence of charge can be used to interpret particular information. This is similar to the principle used in dynamic memories and it brings the same benefits of simpler an...

A new method for the time-domain solution of general nonlinear dynamic circuits is presented. In this method, the solutions of the state variables are computed by using their time derivatives up to some order at the initial time instant. The computation of the higher order derivatives is equivalent to solving the same linear circuit for various sets of DC excitations. Once the time derivatives ...

This work studies the effects of dynamic threshold design techniques on the speed and power of digital circuits. A new dynamic threshold transistor structure has been proposed to improve performances of digital circuits. The proposed switched-capacitor dynamic threshold PMOS (SC-DTPMOS) scheme employs a capacitor along with an NMOS switch in order to effectively reduce the threshold voltage of ...