Considerable challenges are encountered when bulk CMOS devices are scaled into the sub-100 nm regime for higher integrated circuit (IC) density and performance. Due to their excellent scalability and better immunity to short channel effects, double-gate (DG) MOSFETs are being easily assessed for CMOS applications beyond the 70 nm of the SIA roadmap. For channel lengths below 100 nm, DG MOSFETs ...

The variation of the temperature-dependent performance an electronic device is one major concerns in predicting actual electrical characteristics as bandgap semiconducting material varies with temperature. Therefore, this article, we investigate impact temperature variations ranging from 300 to 450K on DC, analog/ radio frequency, and linearity dual stack gate oxide-source dielectric pocket-tun...

Abstract Multi-gate MOSFETs are considered for realizing ultra-low-power circuits due to their superior channel control capability and short effect (SCE) resistance. To achieve this goal, it is necessary establish a suitable compact device circuit model them. However, current research focuses more on single-material multi-gate MOSFET, there no report dual-material logic gates. In work, we devel...

Abstract In the nanoscale regime, the double-gate MOSFET can provide superior short-channel behavior. For this structure, device scaling issues are explored. Gate length scaling will be limited by the ability to control off-state leakage current due to quantum tunneling and thermionic emission between the source and drain as well as band-to-band tunneling between the body and drain. Lateral S/D...

Abstract In recent years, label-free sensors have been studied extensively for biomolecule detections. Label-free biosensors based on MOSFETs could achieve high detection sensitivity, the subthreshold swing of such cannot break limitation 60 mV Dec −1 due to physical mechanism thermal electron emission. However, less than can be achieved in tunnel FETs working band tunneling (BTBT) mode. Usuall...

Nowadays, the development of VLSI technology is mainly directed towards the miniaturization of semiconductor devices which in turn is heavily dependent on the advancement in the CMOS technology. The minimum dimension of a single device for present day technology is below sub-100 nm in channel length. As CMOS technology dimensions are being aggressively scaled down to the fundamental limits (suc...

In this article, a new structure is presented for MOS (Metal Oxide Semiconductor)-like junctionless carbon nanotube field effect transistor (MOS-like J-CNTFET), in which dual material gate with different work-functions are used. In the aforementioned structure, the size of the gates near the source and the drain are 14 and 6 nm, respectively, and the work-functions are equal and 0.5 eV less tha...