This paper describes a preliminary compiler based approach to achieving high performance DSP applications by automatically mapping C programs to multi-processor DSP systems. DSP programs typically contain pointer based memory accesses making automatic parallelisation difficult. This paper presents a new method to convert a restricted class of pointer-based memory accesses into array accesses wi...

DSP processor growth is phenomenal and continues to grow rapidly, but general-purpose microprocessors have entered the multimedia and signal processing oriented stream by adding DSP functionality to the instruction set and also providing optimized assembly libraries. In this paper, we compare the performance of a general-purpose processor (Pentium II with MMX) versus a DSP processor (TI’s C62xx...

In order to save numerous man power hours fritter away to monitor various process parameters in industries whole day, the design presented in this paper gives solution to acquire data at desired rate and monitor fault with alarm system. The design introduces wireless information flow between on field acquisition and remote monitoring part at the office. DSP processor TMS320F2812 which is a very...

A sophomore level introductory Digital Signal Processing (DSP) architecture course introduces students to concepts of DSP while teaching processor structure and organization and the processor language. This class does not assume that the students have already completed a linear systems class as prerequisite knowledge. Instead it is based on material traditionally taught in the introductory circ...

D eveloping a single-processor platform is bad enough. Adding another to the mix could drive even the best developers over the edge, especially when the mix involves a general-purpose processor (GPP) and a DSP. Take heart. A new way of thinking and working allows DSP processes to make operating system calls that are processed by the GPP. Likewise, the operating system running on the GPP can con...

This paper describes the C-NNAP machine, a MIMD implementation of an array of ADAM binary neural networks, primarily designed for image processing. C-NNAP comprises an array of VME cards each containing a DSP, SCSI controller and the SAT peripheral processor. The SAT processor is a dedicated hardware implementation that performs binary neural network computations. The SAT processor yields a spe...

Recent strides in programmable logic density, speed and hardware description languages (HDL’s) have empowered the engineer with the ability to implement digital signal processing (DSP) functionality within programmable logic devices (PLD’s or FPGA’s). This paper, written for the intermediate DSP engineer or logic designer, begins with an overview of general DSP concepts. Filter design principle...

This thesis considers the design of wireless communications systems which are implemented as highly integrated embedded systems comprised of a mixture of hardware components and software. An introductionary part presents digital communications systems, classification of processors, programmable digital signal processing (DSP) processors, and development and implementation of a flexible DSP proc...

DSP-128 is a new multithreaded stream cipher based on the intractability of the Discrete Logarithm Problem (DLP) with key size of 128-bit. The design of DSP-128 is divided into three stages: Initialization Stage, Keystream Generation Stage, and Encryption Stage. The design goal of DSP-128 is to come up with a secure stream cipher with good performance for data encryption. The experimental resul...

This paper presents the hardware design of a real time tracking system based on DSP/FPGA regarding the research and development of a certain type of short range defence radar. In this tracking system, the FPGA is used as a floating point co-processor of the fixed point DSP, and the large amount of calculation of the debiased converted measurement Kalman Filter (DCMKF) algorithm is realized in F...