We propose and demonstrate self-aligned Double Injection Function Thin Film Transistor (DIF-TFT) architecture that mitigates short channel effects in 200 nm on non-scaled insulator (100 SiO 2 ). In this conceptual design, a combination of ohmic-like injection contact high injection-barrier metal...

In this paper, we propose a novel design analysis for a Junctionless Double Gate Vertical MOSFET (JLVMOS) with metal gate electrode and HfO2, for which the simulations have been performed using TCAD (ATLAS), The simulated results exhibits significant improvements in comparison to conventional JLVMOS device with a polysilicon gate electrode and ITRS values for different node technology . In plac...

In this paper it has been demonstrated that a shielded channel made by varying the side gate length in silicon-on-nothing junctionless transistor not only improves short effect but also improve performance of CMOS circuits device. The proposed device dual stack silicon on nothing (SCDGSSONJLT) drain induced barrier lowering (DIBL), cut-off frequency and subthreshold slope are improved 20%, 39% ...

This paper is investigated the low frequency noise behavior in subthreshold regime of gate-all-around silicon nanowire field effect transistors. Downscaling of multi gate structure beyond 50 nm gate length describes the quantum confinement related model. A drain current model has been described for output characteristics of silicon nanowire FET that is incorporated with velocity saturation effe...

Due to the thin InAlN barrier layer, leakage current is a serious problem in InAlN/GaN high-electron-mobility transistors (HEMTs). The InGaN back-barrier can raise conduction band of GaN buffer layer and enhance carrier confinement, resulting reduced current. surface oxidation treatment prior gate deposition form an oxide reduce In this study, using both technologies, record low off (Ioff) high...

A new SONOS flash memory device with recess channel and side-gate was proposed and designed in terms of recess depth, doping profile, and side-gate length for sub-40 nm flash memory technology. The key features of the devices were characterized through 3-dimensional device simulation. This cell structure can store 2 or more bits of data in a cell when it is applied to NOR flash memory. It was s...

This letter demonstrates a p-type raised source-and-drain (raised S/D) junctionless thin-film transistors (JL-TFTs) with a dual-gate structure. The raised S/D structure provides a high saturation current (>1 μA/μm). The subthreshold swing (SS) is 100 mV/decade and the drain-induced barrier lowering (DIBL) is 0.8 mV/V, and the I on/I off current ratio is over 10(8) A/A for L g = 1 μm. Using a th...

In this paper, we compare four SRAM circuits. They are the conventional SRAM1, the SRAM2 with power switches on VSS line, the SRAM3 with switches on VDD line, and the SRAM4 with switches on both VDD and VSS lines, respectively. Among the four SRAMs, the SRAM2 shows the smallest amount of leakage, because its subthreshold leakage is most suppressed by its BODY and Drain-Induced Barrier Lowering ...

For the first time, a deep study of gate control coefficient (αG) effect on CNTFET performance has done in this research. A new, analytical CNTFET simulation along with multiple parameter approach has executed with 3D output in MATLAB and that used it to examine device performance. It is found that, drain current and transconductance increases with high gate control coefficient. On the other ha...

In this paper, we have proposed a novel FinFET with extended body under the poly gate, which is called EB-FinFET, and its characteristic is demonstrated by using three-dimensional (3-D) numerical simulation. We have analyzed and compared it with conventional FinFET. The extended body height dependence on the drain induced barrier lowering (DIBL) and subthreshold swing (S.S) have been also inves...