Agrawal and Vinay [AV08] showed how any subexponential arithmetic circuit can be thought of as a depth four subexponential arithmetic circuit. This unexpected depth reduction to constant depth is in contrast to curcuits in the Boolean setting. The resulting circuit size in this simulation was more carefully analyzed by Korian [Koi12] and subsequently by Tavenas [Tav13]. We provide a simple proo...

We consider the problem of fixed-polynomial lower bounds on the size of arithmetic circuits computing uniform families of polynomials. Assuming the generalised Riemann hypothesis (GRH), we show that for all k, there exist polynomials with coefficients in MA having no arithmetic circuits of size O(n) over C (allowing any complex constant). We also build a family of polynomials that can be evalua...

This paper proposes a new formalism for layout-driven optimization of arithmetic datapaths. It is based on preserving an arithmetic bit level representation of the arithmetic circuit portions throughout various design stages. The arithmetic bit level description takes into account the arithmetic nature of the datapath and facilitates arithmetic reasoning to identify circuit transformations that...

We continue the study of the complexity classes VP(Zm) and ΛP(Zm) which was initiated in [AGM15]. We distinguish between “strict” and “lax” versions of these classes and prove some new equalities and inclusions between these arithmetic circuit classes and various subclasses of ACC.

A method for dividing a polynomial of degree (2n-l) by a precomputed nth degree polynomial in 0(n log n) arithmetic operations is given. This is used to prove that the evaluation of an nth degree polynomial at n+1 arbitrary points can be done in 0(n log^ n) arithmetic operations, and consequently, its dual problem, interpolation of an nth degree polynomial from 2 n+1 arbitrary points can be per...

This paper presents a clock regenerator using two 2 order Σ-Δ (sigma-delta) modulators for wide range of dividing ratio as defined in HDMI standard. The proposed circuit adopts a fractional-N frequency synthesis architecture for PLL-based clock regeneration. By converting the integer and decimal part of the N and CTS values in HDMI format and processing separately at two different Σ-Δ modulator...

Addition is a fundamental arithmetic operation which is used in different applications such as digital signal processing (DSP) and microprocessors. Single bit adder is the main component of any arithmetic circuit. This paper presents the design of new split-path Data Driven Dynamic (sp-D3L) full adder circuit. Power consumption of proposed adder varies from 0.584 nW to 2.914 nW with variation i...

In this work, we show how to garble arithmetic circuits with full active security in the general multiparty setting, secure full-threshold setting (that is, when only one party is assumed honest). Our solution allows interfacing Boolean garbled circuits. Previous works circuit domain focused on two-party or semi-honest and assuming an honest majority – notably, work of Ben-Efraim (Asiacrypt 201...