In this article, a new approach for the efficient design of quantum-dot cellular automata (QCA) circuits is introduced. The main advantages of the proposed idea are the reduced number of QCA cells as well as increased speed, reduced power dissipation and improved cell area. In many cases, one needs to double the effect of a particular inter median signal. State-of-the-art designs utilize a kind...

In this paper a new design of full adder cell based on Sense Energy Recovery concept using novel exclusive NOR gates is presented. Low-power consumption and delay are targeted in implementation of our design. The circuit designed is optimized for low power at 0.18-μm and 0.09 μm CMOS process technologies in full custom environment. The new circuit has been compared to the existing work based on...

In this paper, a full adder cell based on majority function using Carbon-Nanotube Field-Effect Transistor (CNFET) technology is presented. CNFETs possess considerable features that lead to their wide usage in digital circuits design. For the design of the cell input capacitors and inverters are used. These kinds of design method cause a high degree of regularity and simplicity. The proposed des...

The fused floating-point three-term adder performs two additions in a single unit to achieve better performance and better accuracy compared to a network of traditional floating-point two-term adders, which is referred to as a discrete design. Here are several critical design issues for the fused floating-point three-term adder: 1) Complex exponent processing and significand alignment, 2) Compl...

MOS current mode logic (MCML) techniques are usually used for high-speed applications such as high speed processors and multiplexers for optical transceivers. A new design of full adder is proposed based on MOS Current Mode Logic (MCML). It is a new alternative for designing a full adder. Using MCML logic, the power consumptions of circuits can be reduced to the effective level by supplying it ...

Reversible logic circuits have emerged as a promising technology having its applications in low power CMOS, Quantum Computing, nanotechnology, and optical computing. Power is the major constraint for any circuit Each circuit demands not only low power, but fast speed. This paper is focused on the efficient design of the full Adder/Subtractor with the help of half adder subtractor with single co...

This paper presents a comparative study of different redundant binary full adders (Plus-Plus-Minus (PPM) adder). These PPM adders are simulated to evaluate their performance in total power dissipation, speed and PDP. The performances of these circuits are based on 180nm process model at a supply voltage of 1.8V. We also proposed a new design for PPM adder using 13-transistors. The simulation re...

In this paper, a novel quantum-dot cellular automata (QCA) adder design is presented that reduces the number of QCA cells compared to previously reported designs. The proposed one-bit QCA adder structure is based on a new algorithm that requires only three majority gates and two inverters for the QCA addition. By connecting n one-bit QCA adders, we can obtain an n-bit carry look-ahead adder wit...

In’this paper, a new family of dynamic logic gates called Dualrail DataDriven Dynamic Logic (D4L) is introduced. In this logic family, the synchronization clock signal has been eliminated and correct precharge and evaluation sequmcing is maintained by appropriate use of data instances. The methodology and characteristics of d L are demonstrated in the design of a CLA 32-b adder and a 17-b high-...

Adders, as one of the major components of digital computing systems, have a strong influence on their performance. There are various types of adders, each of which uses a different algorithm to do addition with a certain delay. In addition to low computational delay, minimizing power consumption is also a main priority in adder circuit design. In this paper, the proposed adder is divided into s...