Over-sampling sigma-delta analog-to-digital converters (ADCs) are one of the key building blocks of state of the art wireless transceivers, especially with the voice communication system. This paper addresses a brief review for designing a Sigma-Delta modulator. A Genetic Algorithm (GA) based 2 order Sigma-Delta modulator design is proposed.

This paper describes a new firstand second-order delta-sigma modulator concept where the first integrator is extracted and implemented by a frequency modulator with the modulating signal as the input. The result is a simple delta-sigma modulator with no need for digital-to-analog converters, allowing straight-forward multi-bit quantization. Without the frequency modulator, the circuit becomes a...

A Low power discrete time sigma delta ADC consisting of a second order sigma delta modulator and third order Cascaded Integrated Comb (CIC) filter is proposed. The second order modulator is designed to work at a signal band of 20K Hz at an oversampling ratio of 64 with a sampling frequency of 2.56 MHz. It achieves a signal to noise ratio of 85.2dB and a resolution of 14 bits. The CIC digital fi...

This paper presents a complete set of SIMULINK ® models, which allow exhaustive behavioral simulations of any sigma-delta modulator to be performed. The proposed set of models takes into account most of the sigma-delta modulator non-idealities, such as sampling jitter, kT/C noise and operational amplifier parameters (noise, finite gain, finite bandwidth, slew-rate and saturation voltages). For ...

IEEE Trans. Circuits Syst II, vol. 48, no. 3, pp. 233{244, March 2001 Stability and Performance Analysis of an Adaptive Sigma Delta Modulator Mansour A. Aldajani, Student Member, IEEE, and Ali H. Sayed, Fellow, IEEE Abstract| This work develops an adaptive sigma delta modulator that is based on adapting the quantizer stepsize using estimates of the quantizer input rather than the modulator inpu...

Switched capacitor (SC) based modulator is prone to various non-idealities; especially at the circuit designing stage where the integrator plays an important role and effects the overall performance of the sigma delta modulator. The non idealities take account of sampling jitter which includes the effect of switching circuitry, sampling noise. Opamp parameter include noise, finite dc gain, fini...

A passive 2nd-order sigma-delta modulator based on a cascade of first-order lowpass filters was designed, fabricated, and tested. A lumped RC filter is added in the loop of a conventional 1st-order passive sigma-delta modulator in order to improve the linearity of its transfer function. A low power edge-triggered comparator was designed and fabricated along with lumped components in ON Semicond...

This paper deals with a system-level optimization of a back-end of audio signal processing chain for hearing-aids, including a sigma-delta modulator digital-to-analog converter (DAC) and a Class D power amplifier. Compared to other stateof-the-art designs dealing with sigma-delta modulator design for audio applications we take the maximum gain of the modulator noise transfer function (NTF) as a...

This paper presents the design of a low power second-order continuous-time sigma-delta modulator for low power applications. The loop filter of this modulator has been implemented based on the nonlinear transconductance-capacitor (Gm-C) by employing current-mode technique. The nonlinear transconductance uses floating gate MOS (FG-MOS) transistors that operate in weak inversion region. The propo...

This paper explains the design of two stage operational amplifier, single bit comparator and D flipflop best suited for the fifth order continuous-time sigma-delta modulator. A fifth order continuous time sigma delta modulator is chosen for 40MHz Signal Bandwidth with an nyquist frequency of 150MHz. Two stage opamp is used to provide the high gain to the modulator. A single quantizer is used to...