Sequential graph partitioning algorithms have been developed to fulfill the requirements of emerging multi-phase problems in circuit delay models. In this paper we propose a heuristic algorithm for kpartition, which minimizes the circuit delay and cut size. Experimental results with MCNC benchmark circuits have shown that the delay in the circuit can be reduced by marginally in comparison with ...

A novel technique for a self-equalized distributed amplifier is presented by showing the analogy between transversal filters and distributed amplifier topologies. The appropriate delay and gain coefficients of amplifier circuit are obtained by a Fourier expansion of the raised cosine spectrum in the frequency range of 0-40GHz.

This work investigates the channel thickness dependency of high-k gate dielectric-based complementary metal-oxide-semiconductor (CMOS) inverter circuit built using a conventional double-gate metal gate oxide semiconductor field-effect transistor (DG-MOSFET). It is espied that the use of high-k dielectric as a gate oxide in n/p DG-MOSFET based CMOS inverter results in a high noise margin as well...

A Delay-Locked Loop (DLL) with a modified charge pump circuit is proposed for generating high-resolution linear delay steps with sub-picosecond jitter performance and adjustable delay range. The small-signal model of the modified charge pump circuit is analyzed to bring forth the relationship between the DLL's internal control voltage and output time delay. Circuit post-layout simulation shows ...

This paper presents the design, layout, and testability analysis of delay-insensitive circuits on cellular arrays for nanocomputing system design. In delay-insensitive circuits the delay on a signal path does not affect the correctness of circuit behavior. The combination of delayinsensitive circuit style and cellular arrays is a useful step to implement nanocomputing systems. In the approach p...

A Delay-Locked-Loop with a quasi-linear modified differential delay element is presented. By employing body feed technique in the bias circuit of delay cell in the Multi-Controlled-Delay-Line, applicable range for the controlled signal has been widen to under-threshold voltages, also the nonlinearity of the conventional current starved delay element the has been suppress by bias circuit. Moreov...

-The present paper reports a first order nonlinear retarded type time-delayed chaotic and hyperchaotic electronic circuit. The proposed circuit has three distinct advantages over the existing time-delayed circuits. First, it has a nonlinearity that is expressed by closed form mathematical functions, which makes the analysis and design of the circuit easier. Second, the time-delay part of the pr...

We propose a resynthesis method that modifies a given circuit to reduce the number of paths in the circuit and thus improve its path delay fault testability. The resynthesis procedure is based on replacing subcircuits of the given circuit by structures called comparison units. A subcircuit can be replaced by a comparison unit if it implements a function belonging to the class of comparison func...