Recent technology trends have emphasized low power, single supply operation. The LT1016, although capable of such operation, does not include ground in its input range. As such, it must be biased into its operating common mode range for practical single supply use. A new device, the LT1394, maintains the speed and application civility of its predecessor while including ground in its input opera...

Abstract — The design and various analysis of low power, high speed CMOS dynamic latch comparator is presented. The comparator combines the features of both, the resistive dividing network and differential current sensing comparator. The proposed design will improve the comparator performance by reducing the propagation delay, power dissipation, offset with high ICMR. Simulation results are obt...

High-speed 64-bit binary comparator using two different logic styles is proposed in this brief. Comparison is most basic arithmetic operation that determines if one number is greater than, equal to, or less than the other number. Comparator is most fundamental component that performs comparison operation. This brief presents comparison of modified and existing 64-bit binary comparator designs c...

High-speed 64-bit binary comparator using three stages with CMOS logic style is proposed in this brief. Comparison is most basic arithmetic operation that determines if one number is greater than, equal to, or less than the other number. Comparator is most fundamental component that performs comparison operation. This brief presents comparison of modified and existing 64-bit binary comparator d...

The design of high gain, wide dynamic range op-amps for switched-capacitor circuits has become increasingly challenging with the migration of designs to scaled CMOS technologies. The reduced power supply voltages and the low intrinsic device gain in scaled technologies offset some of the benefits of the reduced device parasitics. An alternative comparator-based switched-capacitor circuit (CBSC)...

quantum-dot cellular automata (qca) is an emerging and promising technology that provides significant improvements over cmos. recently qca has been advocated as an applicant for implementing reversible circuits. however qca, like other nanotechnologies, suffers from a high fault rate. the main purpose of this paper is to develop a fault tolerant model of qca circuits by redundancy in hardware a...

The need for low power, high speed Analog-To-Digital converters is pushing towards the use of dynamic comparator to maximize speed &power efficiency. In this paper, we designed a Dynamic Latched Double-Tail Comparator which is used in implementation of many ADC’s. An analysis on the delay of the comparator will presented. Simulation results in 0.18um CMOS technology confirm the analysis results...

A CMOS current comparator with well-controlled hysteresis is described. The current comparator allows bidirectional input currents. Expcrimental results show that the current comparator takes approximately 300 ns to rcsolve a 2 KA difference of input and threshold currents.

This paper explores various available comparator designs and proposes an improved ultra low power comparator with reduced delay at 90nm. Dynamic comparators which are extensively used in data converters and digital signal processors require low power consumption and high speed. A clock based dynamic comparator is simulated with delay of 64ps and power dissipation of 31.8μW. The comparator struc...

A high-speed 64-bit binary comparator is proposed in this brief. Comparison is most basic arithmetic operation that determines if one number is greater than, equal to, or less than the other number. Comparator is most fundamental component that performs comparison operation. This brief presents comparison of modified and existing 64-bit binary comparator designs concentrating on delay. Means so...