This paper presents a novel methodology of simulation and realization of a various Op-amp topologies, such as two-stage, telescopic and folded cascade are discussed in this paper. The aim of the present work is the development of a tool box which contains the Matlab code to allow automated synthesis of Analog circuits. This tool box is used to find the transistor dimensions (i.e.., width and le...

We are developing low power cryogenic readout integrated circuits (ROICs) for large format far-infrared image sensors using fully-depleted-silicon-on-insulator (FD-SOI) CMOS technology. We have evaluated the characteristics of MOS FETs fabricated by the FD-SOI CMOS technology and have found that both p-ch and n-ch FETs show good static performance below the liquid helium temperature, where n-ch...

A new design approach for three-stage operational amplifiers (op-amps) is proposed. It allows to actually implement a symmetrical push-pull class-AB amplifier output stage for wellestablished three-stage amplifiers using a feedforward transconductance stage. Compared with the conventional design practice, the proposed approach leads to a significant improvement of the symmetry between the posit...

As CMOS technology continues to evolve, the supply voltages are decreasing while at the same time the transistor threshold voltages are remaining relatively constant. Making matters worse, the inherent gain available from the nano-CMOS transistors is dropping. Traditional techniques for achieving high gain by vertically stacking (i.e. cascoding) transistors becomes less useful in sub-100nm proc...

The performances of two full differential operational amplifiers (Op-Amps) telescopic and foldedcascode are evaluated to satisfy the stringent requirements on the amplifier to be used in a Multiplying Digitalto-Analog Converter (MDAC) stage of a pipelined ADC (Analog-to-Digital Converter). The paper shows the solutions found to reach high gain, wide bandwidth and short settling time without deg...

Cascode CMOS op-amps use a large number of external bias voltages. This results in numerous drawbacks, namely, an area and power overhead, susceptiblity of the bias lines to noise and cross-talk and high sensitivity of the bias point to process variations. In this paper we present a self-biasing technique for folded cascode CMOS op-amps that uses no additional devices and no baas voltages other...

Operational Amplifier (op-amp) is a basic building block of many analog and mixed signal systems. Many different types of op-amp are used to achieve various functions, such as DC biasing, high speed amplifying, reduced voltage supply, high gain. To achieve these parameter successfully there are several techniques.The op-amp contains two stages to increase gain and improve slew rate, voltage swi...

Before venturing further on the design of our operational amplifier, the first line of business is to determine the optimal topology for the given specifications. The factor that clearly stands out is the high dynamic range requirement of 85 db. Several topologies are given for this task, among these telescopic op-amp is selected. Compensation techniques are used with two stage topology of tele...

A technique for low-voltage CMOS analog circuit design is presented in this paper. In this technique, voltage sources are added in series with the gates of the MOS transistors to lower the effective threshold voltages of the transistors. With the lowered effective threshold voltage, it is possible to build a host of analog circuit that operates with a decreased supply voltage. A 0.6V ultra-low ...

A high-swing, high-performance CMOS telescopic operational amplifier is described. The high swing of the op-amp is achieved by employing the tail and current source transistors in the deep linear region. The resulting degradation in differential gain, common-mode rejection ratio (CMRR), and other amplifier characteristics are compensated by applying regulatedcascode differential gain enhancemen...