This paper presents a noise reduction technique using common-mode feedback in active CMOS mixers. The proposed decreases the noise, thus reducing common-to-differential conversion arising from mismatch and process variations. In addition, reduces sensitivity to process, voltage, temperature (PVT) variations due negative feedback. A theory is adopted analyze low-noise performance of technique. t...

This paper presents a Q-band image-rejection receiver using 65 nm CMOS technology. For high ratio (IMRR), the employs Hartley architecture which consists of low-noise amplifier, two down-conversion mixers, 90° hybrid coupler, and IF baluns. In addition, fundamental voltage-controlled oscillator (VCO) frequency divider chain divided by 256 are integrated into for LO. A charge injection technique...

Modern wireless transceivers are required to operate over a wide range of frequencies in order to support the multitude of currently available wireless standards. Wideband operation also enables future systems that aim for better utilization of the available spectrum through dynamic allocation. As such, co-existence problems like harmonic mixing and phase noise become a main concern. In particu...

A 2-GHz direct digital frequency synthesizer (DDFS) chip-set is presented which operates at a very low supply voltage of 2 V. The chip-set consists of a CMOS DDFS-large scale integrator (LSI) which synthesizes a sine wave at 55 Msps with an internal 10-b digital-to-analog converter (DAC) and Si-bipolar image-reject up-converters. To achieve both high purity and low power dissipation, we develop...

This paper presents a low voltage wideband downconversion mixer using current-mode approach for multi-standard receivers. The proposed mixer uses a current mirror amplifier with an embedded passive switching core to achieve mixing function, which can combine the advantages of active and passive mixers simultaneously. The mixer is implemented using a 0.18μm CMOS technology and covers frequency b...

A new analytical model for high-frequency noise in RF active CMOS mixers such as single-balanced and doublebalanced architectures is presented. The analysis includes the contribution of non-white gate-induced noise at the output as well as the spot noise figure (NF) of the RF CMOS mixer, while accounting for the non-zero correlation between the gateinduced noise and the channel thermal noise. T...

In this paper a 3.5 GHz down conversion mixer with 20 MHz IF output signal for location-fixed WiMAX systems is presented. The proposed mixer is implemented with TSMC 0.18μm RF CMOS technology with 1.5V supply voltage which utilizes Current-Bleeding and Current-Reuse techniques to improve noise figure and conversion gain of conventional Gilbert-type structure. This mixer achieves 12 dB of conver...

The design of a CMOS 22–29-GHz pulse-radar receiver (RX) front-end for ultra-wideband automotive radar sensors is presented. The chip includes a low-noise amplifier, in-phase/quadrature mixers, a quadrature voltage-controlled oscillator (QVCO), pulse formers, and baseband variable-gain amplifiers. Fabricated in a 0.18m CMOS process, the RX front-end chip occupies a die area of 3 mm . On-wafer m...

A CMOS quadrature down-converter for a direct-conversion receiver of 5.15-5.825GHz wireless LAN is described. The down-converter consists of two sub-harmonic mixers, for I and Q channels, and an LO generation network. In order to prevent the low-frequency component generated by the even-order distortion of the transconductance stage from being leaked to the mixer output, transconductance and sw...

A 2.4 GHz CMOS up-conversion mixer using novel current mirrors based on chartered 0.18 μm RF CMOS technology for 2.4 GHz wireless sensor network (WSN) application is presented in this paper. The current-reuse current-mirror and current-bleeding technique are used in the driver and switching stages of the mixer, respectively. The post-layout simulation results demonstrate that the novel up-conve...