By offering zero standby power, non-volatile logic is a promising solution to overcome the leakage losses which have become an important obstacle to scaling of CMOS technology [1]. Magnetic tunnel junctions (MTJs) offer a great potential, because of their unlimited endurance, CMOS compatibility, and fast switching speed. Recently, several realizations of MTJ-based logic gates have been demonstr...

The current status of High K dielectrics in Very Large Scale Integrated circuit (VLSI) manufacturing for leading edge Dynamic Random Access Memory (DRAM) and Complementary Metal Oxide Semiconductor (CMOS) applications is summarized along with the deposition methods and general equipment types employed. Emerging applications for High K dielectrics in future CMOS are described as well for impleme...

I N THE quest of a potential alternative to CMOS at the end of its roadmap, multitude of research efforts have been directed towards investigating novel devices with unique characteristics. These emerging devices hold tremendous potential in achieving higher integration density (in the order of devices/cm), higher performance, and increased energy efficiency for computation. On the other hand, ...

Metrics of energy, area, and time are defined Cor a graphthe<>retic model of \'LSI computation. Different "constant factors" are se1'n to. be appropriate for different logic families. We ex amine seven such familie!l: NMOS, CMOS, CMOS-SOS, J2L, Gru\s liEMT, JJ-CrL, and JJ-CS. For each family, we sketch a construction f6r an energy-efficient, read/write, random-access memory circuit.

The Switched-Current (SI) technique is a circuit method that enables analog sampled-data circuits to be realized with a standard digital CMOS process. At this time it is fair to say that SI circuits are realized from either rstor second-generation type current memory cells, with the latter cell being favored owing to its perceived better sensitivity behavior. Unfortunately, however, the second-...

Abstract An implementation in CMOS technology of a Floating-Gate Analog Memory Cell and Programming Environment is presented. A digital closed-loop control compares a reference value set by user and the memory output and after cycling, the memory output is updated and the new value stored. The circuit can be used as analog trimming for VLSI applications where mechanical trimming associated with...

An analog CMOS peak detect and hold (PDH) circuit, which combines high speed and accuracy, rail-to-rail sensing and driving, low power, and buffering is presented. It is based on a configuration that cancels the major error sources of the classical CMOS PDH, including offset and common mode gain, by re-using the same amplifier for tracking, peak sensing, and output buffering. By virtue of its h...

FinFET memory is widely used in various semiconductor products due to its good read/write margin, lower power consumption, and faster driving speed. However, the forked 3D physical structure increased density of storage are very susceptible manufacturing defects, which may cause functional logic faults that different from traditional planar CMOS memories. Therefore, it critical explore an effec...

The performance of a Hamming Distance Classiier based on static memory cells and an analog winner-takes-all circuit depends on device matching in the various parts of the circuit. This dependence has been analyzed, leading to design criteria for choosing the device sizes and chip structure. The theoretical performance of a CMOS chip designed to operate in the subthreshold region has been compar...