in this paper a novel design of all-optical half-subtractor based on nonlinear directional coupler is proposed. by using four waveguides and appropriately adjusting the refractive indices and selecting the proper length of waveguides, halfsubtractor function can be obtained. the operation of this function is simulated by rsoft cad-layout (beamprop) simulator. the simulation results confirm the ...

The design process for VLSI systems requires several iterations of the physical design cycle. After a partitioning of the circuit and a floorplanning step, the circuit components are placed. The wires between the components are then routed taking the placement into account. A bad placement cannot be solved by a good routing. Therefore, the information obtained during routing generally leads to ...

We use evolutionary search to design combinational logic circuits. The technique is based on evolving the functionality and connectivity of a rectangular array of logic cells whose dimension is defined by the circuit layout. The main idea of this approach is to improve quality of the circuits evolved by the genetic algorithm (GA) by reducing the number of active gates used. We accomplish this b...

The proposed multiplexer-based novel 1-bit full adder cell is schematized by using DSCH2 and its layout is generated by using microwind VLSI CAD tool. The adder cell layout interconnect analysis is performed by using BSIM4 layout analyzer. The adder circuit is compared with other six existing adder circuits for parametric analysis. The proposed adder cell gives better performance than the other...

This paper describes a knowledge-based system for automatically synthesizing integrated circuit layouts for NMOS cells. The desired cell layouts are specified in terms of their general structural and functional characteristics. From these initial specifications, the system produces correct and CoriJpact cell layouts. The system performs this task by generating plan steps at different levels of ...

For submicron integrated circuits, 3D numerical techniques are required to accurately compute the values of the interconnect capacitances. In this paper, we describe an hierarchical capacitance extraction method that efficiently extracts 3D interconnect capacitances of large regular layout structures such as RAMs and array multipliers. The method is based on a 3D capacitance extraction method t...

Today, layout verification for VLSI is a crucial part of IC design. However, for applicability, this must be both fast and accurate. Layout-to-circuit extractors can meet both these constraints. They quickly convert a layout into an equivalent network that accurately models that layout. Subsequently, circuit simulation and network comparison are convenient tools that enable accurate prediction ...

Quantum-dot Cellular Automata (QCA) is an emerging and promising technology that provides significant improvements over CMOS. Recently QCA has been advocated as an applicant for implementing reversible circuits. However QCA, like other Nanotechnologies, suffers from a high fault rate. The main purpose of this paper is to develop a fault tolerant model of QCA circuits by redundancy in hardware a...

In this paper, a new low-VDD CMOS bandgap reference circuit with small layout area and low power consumption is proposed. The proposed circuit delivering its output voltage below 1V has its Proportional-To-Absolute-Temperature (PTAT) term compensated by the Complementary-proportional-To-AbsoluteTemperature (CTAT) voltage thereby suppressing a change in its output voltage regardless of temperatu...