نتایج جستجو برای: carry look ahead adder
تعداد نتایج: 167513 فیلتر نتایج به سال:
Efficiency of adiabatic circuits is determined by the adiabatic and non-adiabatic losses incurred by them during the charging and recovery operations. Lesser be the losses more energy efficient would be the circuit. In this paper, a new approach i.e., Complementary Energy Path Adiabatic Logic (CEPAL), is presented to minimize power dissipation in quasi static energy recovery logic (QSERL). It o...
Continuous scaling of the transistor size and reduction of the operating voltage has led to a significant performance improvement of integrated circuits. Low power consumption and smaller area are some of the most important criteria for the fabrication of DSP systems and high performance systems. In this paper there is try to determine the best solution to this problem by comparing a few adders...
The efficient implementation of adders in differential logic can be carried out using a new generate signal (N ) presented in this paper. This signal enables iterative shared transistor structures to be built with a better speed/area performance than a conventional implementation. It also allows adders developed in domino logic to be easily adapted to differential logic. Based on this signal, t...
This paper proposed a new method for adding sum and carry using carry look-ahead adder at the final stage of the radix-8 booth decoding multiplier. In a conventional radix-8 booth decoded multiplier, full adders and half adders are used to add sum and carry. After partial product reduction using booth decoding, the partial product rows are required to add for final result. In this method carry ...
This paper presents the design and implementation of a time driven adder generator architecture. There exists a large variety of adders designed to satisfy different computation requirements, in particular we list the Carry Look Ahead (CLA) adder, the skip adder, the ripple adder, the carry select adder (CSA), etc. These different architectures will offer different delays and it is up to the us...
Abstract-Low-voltage and low-power circuit structures are substantive for almost all mobile electronic gadgets which generally have mixed mode circuit structures embedded with analog sub-sections. Using the reconfigurable logic of multiinput floating gate MOSFETs, 4-bit full adder has been designed for 1.8V operation. Multi-input floating gate (MIFG) transistors have been anticipating in realiz...
Addition is the fundamental operation for any VLSI processors or digital signal processing. In this paper focuses on carry -look ahead adders have done research on the design of high-speed, low-area, or low-power adders. Here domino logic is used for implementation and simulation of 128 bit Carrylook ahead adder based HSPICE Tool. In adder circuits propagation delay is the main drawback. To ove...
With the growing importance of electronic products in day-to-day life, the need for portable electronic products with low power consumption largely increases. In this paper, an area efficient high speed and low power Multiply Accumulator unit (MAC) with carry look-ahead adder (CLA) as final adder is being designed. In the same MAC architecture design in final adder stage of partial product unit...
Adders, as one of the major components of digital computing systems, have a strong influence on their performance. There are various types of adders, each of which uses a different algorithm to do addition with a certain delay. In addition to low computational delay, minimizing power consumption is also a main priority in adder circuit design. In this paper, the proposed adder is divided into s...
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