The increasing growth of sub-micron technology has resulted in the difficulty of testing. Design and test engineers have left no choice but to accept new responsibilities that had been performed by group of technicians in the previous years. Design engineers who do not design systems with full testability had increased the possibility of product failures and missed market opportunities. BIST is...

This paper discusses practical issues involved in applying logic built-in self-test (BIST) to four large industrial designs. These multi-clock designs, ranging in size from 200K to 800K gates, pose significant challenges to logic BIST methodology, flow, and tools. The paper presents the process of generating a BIST-compliant core along with the logic BIST controller for at-speed testing. Compar...

True software-defined radio cellular base stations require extremely fast data converters, which can currently not be implemented in semiconductor technology. Superconductor Niobium-based delta ADCs have shown to be able to perform this task. The problem of testing these devices is a severe task, as still very little is known about possible defects in this technology. This paper shows an approa...

Marco d’Ischia 1,* ID and Daniel Ruiz-Molina 2,* ID 1 Department of Chemical Sciences, University of Naples Federico II, Via Cintia 4, I-80126 Naples, Italy 2 Catalan Institute of Nanoscience and Nanotechnology (ICN2), CSIC and BIST, Campus UAB, Bellaterra, 08193 Barcelona, Spain * Correspondence: [email protected] (M.d.I); [email protected] (D.R.-M.); Tel.: +39-081-674132 (M.d.I.); +34-093-737...

Makassar is one of the metropolitan cities located in Indonesia which recently experiences massive an increased construction because of population growth. Mapping the spatial distribution and development of the built-up region is the best method that can use as an indicator to set the urban planning policy. The purpose of this study is to identify changes in land use and density in Makassar Cit...

1.1 1:30 p.m. "An Efficient Self-Test Structure for Sequential Machines" S.Z. Hassan Rolm Mil-Spec Computers In this paper, a BIST structure for sequential machines is presented. The approach requires augmentation of the machine by the addition of an extra input and some logic. The test sequence is independent of the function implemented and depends only on the number of input combinations and ...

1. Introduction Logic Built-In Self-Test (BIST) schemes based on STUMPS structure use on-chip circuitry to generate test stimuli and analyze test responses, with little or no help from an ATE. The STUMPS (Self-Test Using a MISR and Parallel Shift register sequence generator) structure applies pseudo-random patterns generated by a PRPG (Pseudo-Random Pattern Generator) to a full-scan circuit in ...

Built-in self-test (BIST) is an attractive approach to detect delay faults because of its inherent support for at-speed test. Deterministic logic BIST (DLBIST) is a technique that has been successfully applied to stuck-at fault testing. As delay faults have lower random pattern testability than stuck-at faults, the need for DLBIST schemes has increased. However, an extension to delay fault test...

This paper deals with Hybrid multisite testing of VLSI chips by utilizing automatic test equipment (ATE) in connection with built-in self-test (BIST). The performance of a multisite testing process is analyzed using device-under-test (DUT) parameters (such as yield and average number of faults per DUT) as well as test process features (such as number of channels, coverage and touchdown time for...