In this paper we present high performance dynamically allocated multi-queue (DAMQ) buffer schemes for fault tolerance systems on chip applications that require an interconnection network. Two or four virtual channels shared the same buffer space. On the message switching layer, we make improvement to boost system performance when there are faults involved in the components communication. The pr...

Performance of ATM networks depends on switch performance and architecture. This paper presents a simulation study of a new dynamic allocation of input buffer space in ATM switching elements. The switching elements are composed of input and output buffers which are used to store received and forwarded cells, respectively. Efficient and fair use of buffer space in an ATM switch is essential to g...

The geometric buffer (G-buffer) is a well-known approach to implement imagebased rendering algorithms. We propose a framework that maps the G-buffer concept and associated image-space operations to the graphics processing unit (GPU). This GPU-G-buffer (G-buffer) framework consists of two major components: first, a texture-based representation of the G-buffer attributes; second, an implementatio...

In this paper, we propose a Bi-directional Fragmental Pipelining (BFP) technique and its variable buffer size data-caching scheme BFPV to reduce the disk I/O bandwidth requirement for multimedia servers. Our mathematical analysis shows that the BFP technique is superior to the traditional unidirectional pipelining technique in terms of memory buffer space requirement. We further demonstrate tha...

In a shared buffer packet switch, a good buffer management scheme is needed to reduce the overall packet loss probability and improve the fairness between different users. In this paper, a novel buffer control scheme called partial sharing and partial partitioning (PSPP) is proposed. The PSPP is an adaptive scheme that can be dynamically adjusted to the changing traffic conditions while simple ...

In this paper we present high performance dynamically allocated multi-queue (DAMQ) buffer schemes for fault tolerance systems on chip applications that require an interconnection network. Two virtual channels shared the same buffer space. Fault tolerant mechanisms for interconnection networks are becoming a critical design issue for large massively parallel computers. It is also important to hi...

In this paper, we comparatively evaluate two photonic packet switch architectures with WDM-FDL buffers for synchronized variable length packets. The first one is an output buffer type switch, which stores packets in the FDL buffer attached to each output port. Another is a shared buffer type switch, which stores packets in the shared FDL buffer. The performance of a switch is greatly influenced...

In this paper, we comparatively evaluate two photonic packet switch architectures with WDM-FDL buffers for synchronized variable length packets. The first one is an output buffer type switch, which stores packets in the FDL buffer attached to each output port. Another is a shared buffer type switch, which stores packets in the shared FDL buffer. The performance of a switch is greatly influenced...

Efficient and fair use of buffer space in ATM switch is essential to gain high throughput and low cell-loss performance from the network. A shared buffer architecture associated with threshold based virtual partition among output ports is proposed. Thresholds are updated based on trajfic characteristics on each outgoing link, so as to adapt to traf$c loads. System behavior under varying trafJic...