This paper presents Field Programmable Gate Array (FPGA) implementation of standard and truncated multipliers using Very High Speed Integrated Circuit Hardware Description Language (VHDL). Truncated multiplier is a good candidate for digital signal processing (DSP) applications such as finite impulse response (FIR) and discrete cosine transform (DCT) etc. Significant reduction in FPGA resources...

We present a Matrix-vector form of Karatsuba multiplication over GF (2m) generated by an irreducible trinomial. Based on shifted polynomial basis (SPB), two Mastrovito matrices for different Karatsuba multiplication parts are studied. Then related multiplier architecture is proposed. This design effectively exploits the overlapped entries of the Mastrovito matrices to reduce the space complexit...

Based on the shifted polynomial basis (SPB), a high efficient bit-parallel multiplier for the field GF(2m) defined by an equallyspaced trinomial (EST) is proposed. The use of SPB significantly reduces time delay of the proposed multiplier and at the same time Karatsuba method is combined with SPB to decrease space complexity. As a result, with the same time complexity, approximately 3/4 gates o...

Multiplication is frequently required in digital signal processing. Parallel multipliers provide a high-speed method for multiplication, but require large area for VLSI implementations. In most signal processing applications, a rounded product is desired to avoid growth in word size. Thus an important design goal is to reduce the area requirement of the rounded output multiplier. This paper pre...

A new scheme for the implementation of programmable FIR digital filters with 100% operational efficiency is presented in this paper. The term 100% operational efficiency implies that no zero bits have to be inserted between successive in−put data words in order the filter input to be synchronized with the filter output. Both the input data and the filter out−put are in two’s complement LSB−firs...

Using the self duality of an optimal normal basis (ONB) of type II, we present a bit parallel systolic multiplier over GF (2) which has a low hardware complexity and a low latency. We show that our multiplier has a latency m + 1 and the basic cell of our circuit design needs 5 latches (flip-flops). On the other hand, most of other multipliers of the same type have latency 3m and the basic cell ...