In this work' we develop models of resistive bridging faults and study the fault coverage on ISCAS85 circuits of different test sets using resistive and zero-ohm bridges at different supply voltages. These results explain several previously observed anomalous behaviors. In order to serve as a reference, we have developed the $rst resistive bridging faylt ATPG, which attempts to detect the maxim...

In this paper the ATPG is implemented using C++. This ATPG is based on fault equivalence concept in which the number of faults gets reduced before compaction method. This ATPG uses the line justification and error propagation to find the test vectors for reduced fault set with the aid of controllability and observability. Single stuck at fault model is considered. The programs are developed for...

Empirical observation shows that practically encountered instances of ATP6 are efficiently solvable. However, it has been known for more than two decades that ATPG is an NP-complete problem. This work is one of the first attempts to reconcile these seemingly disparate results. We introduce the concept of circuit cut-width and characterize the complexity of ATPG in terms of this property. We pro...

Automatic Test Pattern Generation (ATPG) is one of the core problems in testing of digital circuits. ATPG algorithms based on Boolean Satisfiability (SAT) turned out to be very powerful, due to great advances in the performance of satisfiability solvers for propositional logic in the last two decades. SAT-based ATPG clearly outperforms classical approaches especially for hard-to-detect faults. ...

Wolfgang Roethig NEC Electronics 2880 Scott Blvd., Santa Clara CA 95052 [email protected] This paper proposes to put power analysis into the scope of high-level ATPG. The similarities between ATPG and simulation vector generation for power analysis have been identified in the past. In both cases, a sequence of simulation vectors is to be generated with maximum toggle count on all relevant net...

——Superconductor logic has the potential of extremely low-power consumption and ultra-fast digital signal processing. Unfortunately, the obtained yield of the present processes is low and specific faults occur. This paper deals with fault-modelling, Design-for-Test structures, and ATPG for these integrated circuits. Index Terms—— Fault modelling, Design-for-Test, Defect Monitor Structures, ATPG

This paper extends state-of-the-art ATPG systems by including constraints, called restrictors, on the allowable values of the bits of a test vector. Such restrictors often occur in ’realworld’ circuits where certain bit positions of a test vector have to take on a particular value (e.g. in case of a reset line) or are prohibited from taking on a particular value (e.g. in order to prevent an ill...

This paper presents a parallel ATPG to speed up the test pattern generation process. The ATPG adopts the master-slave architecture to reduce the inter-process communication. Also, a smart fault list broadcast and fault partition technique is proposed to reduce test pattern inflation. Simulation results show that close to linear speed-up can be achieved for up to 7 slave processes.

We introduce theorems that enable efficient identification of indistinguishable fault pairs in synchronous sequential circuits using an iterative logic array of limited length. These theorems can be used for identifying fault pairs that can be dropped from consideration before diagnostic ATPG starts, thus improving the efficiency of diagnostic ATPG. Experimental results are presented to demonst...