This paper presents an all-digital phase-locked loop (ADPLL) architecture in a new light that allows it to significantly save power through complexity reduction of its phase locking and detection mechanisms. The predictive nature of the ADPLL to estimate next edge occurrence of the reference clock is exploited here to reduce the timing range and thus complexity of the fractional part of the pha...

Nowadays, the All-Digital Phase-Locked Loop (ADPLL) as a digital electronic circuit is applied in modern communication systems. The main components of ADPLL such as phase detector, loop filter and voltage controlled oscillator which are all digitally discussed in detail. On the other hand, sensitivity to parasitic mismatches in LC oscillators and the limitation of the robustness and the quantiz...

This letter proposes a mm-wave fractional-N reference-oversampling (ROS) ADPLL for 5G applications utilizing relatively low but standard reference frequency. The 4× ROS phase detector (PD) increases the detection rate in power-efficient manner order to reduce in-band noise contributed from PD. improves overall FoM and locking speed. A class-F3 oscillator generates both 10 GHz its third harmonic...

This paper proposes a low-power all-digital phase-locked loop (ADPLL) with calibration-free ring oscillator (RO)-based injection-locking time to digital converter (TDC) for BLE applications. The RO is reused as the delay cell of TDC, and quantization step TDC always tracked period; hence no calibration needed in this architecture. We adopt tuning lower bandwidth so decrease power consumption in...

This paper describes the design and implementation of an internet thing (IoT)-based application that uses a true random number generator (TRNG) with all digital phase locked loop (ADPLL) for secure wireless communication. Field programmable gate array (FPGA) boards were used on transmitter receiver sides interfaced Esp8266 chips to wirelessly send receive encrypted sensor data. The MQ-2 gas tra...