Silicon-on-insulator ~SOI! has proven to be a viable alternative to traditional bulk silicon for fabrication of complementary metal–oxide–semiconductor devices. However, a number of unusual phenomena with regards to diffusion and segregation of dopants in SOI have yet to be explained. In the present study, SOITEC wafers were thinned to 700 and 1600 Å using oxidation and etching. Ion implantatio...

Silicon substrate losses and non-linearities were the limiting characteristics of Si-based MOSFET technologies to provide low-power and low-cost solutions to the mobile RF device market. Thanks to the trap-rich Silicon-on-Insulator (SOI) substrate invented at UCL and developed in collaboration with the French company SOITEC, RF SOI is becoming a mainstream technology which is implemented in all...

In this article, a novel concept is introduced to improve the radio frequency (RF) linearity of partially-depleted (PD) silicon-on-insulator (SOI) MOSFET circuits. The transition due to the non-zero body resistance (RBody) in output conductance of PD SOI devices leads to linearity degradation. A relation for RBody is defined to eliminate the transition and a method to obtain transition-free c...

This paper reviews the basic circuit issues of silicon-on-insulator (SOI) technology for metal-oxide-semiconductor (CMOS) circuits. The superior features of SOI in low power, high speed, high device density and the effect of floating body particularly in partial depletion (PD) SOI device are addressed. Analog and RF circuits are considered and their performances are compared with those reported...

OVERVIEW: There is an increased demand for the production of nextgeneration super-high-speed and low-power-consumption CMOS (complementary metal-oxide semiconductor) devices using SOI (silicon on insulator). Major global device manufacturers are actively commercializing this product. In SOI technology, a device is fabricated in a silicon layer (SOI layer) formed on a BOX (buried oxide) film. Al...

The SOI MOSFET technique is used to overcome the scaling effects. In this work, 20nm SOI MOSFET using Poly silicon as gate material of both Ntype and P-type were designed. The same SOI MOSFET is designed using Molybdenum as gate material for both N-type and P-type and the device characteristics werecompared and analysed.

Woodchuck hepatitis virus (WHV) is molecularly and pathogenically closely related to hepatitis B virus (HBV). Both viruses display tropism towards hepatocytes and cells of the immune system and cause similar liver pathology, where acute hepatitis can progress to chronic hepatitis and to hepatocellular carcinoma (HCC). Two forms of occult hepadnaviral persistence were identified in the woodchuck...

Demonstrations of sub 20nm gate length MOSFET devices involving various FEOL (front end of line) schemes such as Silicon On DEpletion Layer (SODEL) FET’s, asymmetricgate FinFET devices, planar Ultra-thin body SOI (UTSOI) FET’s, and, more recently, independently oriented surface channels for (110) pMOS and (100) nMOS described as Simplified Hybrid Orientation Technology (SHOT).[1-4, 718] have be...

The integration of optical functionalities on a chip has been a long standing goal in the optical community. Given the call for more integration, Silicon-on-Insulator (SOI) is a material system of great interest. Although mature CMOS technology can be used for the fabrication of passive optical functionality, particular photonic functions like efficient light emission still require III-V semico...

In this paper, we propose an Active Body-biasing Controlled (ABC)-Bootstrap PTL (Pass-Transistor Logic) on PD-SOI for ultra low power design. Although simply lowering the supply voltage (VDD) causes a lack of driving power, our boosted voltage scheme employing a strong capacitive coupling with ABC-SOI improves a driving power and allows lower voltage operation. We also present an SOI-SRAM desig...