Phase change memory (PCM) is a promising memory technology that can offer higher memory capacity than DRAM. Unfortunately, PCM’s access latencies and energies are higher than DRAM and its endurance is lower. DRAM-PCM hybrid memory systems use DRAM as a cache to PCM, to achieve the low access latencies and energies, and high endurance of DRAM, while taking advantage of the large PCM capacity. A ...

As the technology node of dynamic random-access memory (DRAM) continues to decrease below 10-nm-class, bit-cell failures due external environments have increased. a result, DRAM vendors perform post package inspections provide fault-free DRAMs end customers. However, require considerable test costs. To overcome this issue, an in-DRAM built-in self-test (BIST) mechanism is implemented in study a...

The use of embedded DRAM technology has become widespread, especially in higher-end system designs, because of its superior performance, silicon area savings, and low power compared to discrete memory solutions. Traditionally, in cost-sensitive consumer applications, large memory arrays of 64 megabits and above were usually better suited to discrete commodity memory implementations. But as the ...

Variation has been shown to exist across the cells within a modern DRAM chip. Prior work has studied and exploited several forms of variation, such as manufacturing-processor temperature-induced variation. We empirically demonstrate a new form of variation that exists within a real DRAM chip, induced by the design and placement of different components in the DRAM chip: different regions in DRAM...

Bounding the worst-case DRAM performance for a real-time application is a challenging problem that is critical for computing worst-case execution time (WCET), especially for multicore processors, where the DRAM memory is usually shared by all of the cores. Typically, DRAM commands from consecutive DRAM accesses can be pipelined on DRAM devices according to the spatial locality of the data fetch...

As the main component for modern main memory system, DRAM stores data by capacitors, which must be refreshed periodically to keep the charges. As the size and speed of DRAM devices continue to increase, the overhead of refresh has caused a great power and performance dissipation. In this paper, we proposed a CAM (content-addressable memory)-based Retention-Aware DRAM (CRA-DRAM) system, a hardwa...

Embedded DRAM technology offers many advantages in System On Chip products. Computing applications demand memory with low latency and zero soft error rate. Graphics and networking need high bandwidth. Mobile applications require extremely low power. All applications benefit from the high density afforded by embedded DRAM technology. A single DRAM architecture cannot provide an optimal solution ...

Introduction In the virtual component (VC) integration business, the embedded DRAM is a key VC to realize high bit density and high bandwidth performance, thus the low-cost testing of DRAM-integrated LSI is an emerged problem. The DRAM test usually includes a fail-bit (address) search to repair the memory cell defects with redundancy, requiring long time for wafer probing. A DRAM BIST drastical...

3D-stacked DRAM alleviates the limited memory bandwidth bottleneck that exists in modern systems, by leveraging through silicon vias (TSVs) to deliver higher external memory channel bandwidth. Today’s systems, however, cannot fully utilize the higher bandwidth offered by TSVs, due to the limited internal bandwidth within each layer of the 3D-stacked DRAM. We identify that the bottleneck to enab...

This paper presents a simulation-based performance study of several of the new high-performance DRAM architectures, each evaluated in a small system organization. These small-system organizations correspond to workstation-class computers and use only a handful of DRAM chips (~10, as opposed to ~1 or ~100). The study covers Fast Page Mode, Extended Data Out, Synchronous, Enhanced Synchronous, Do...