Results were previously presented [2] from real-time experiments that evaluated large FPGAs fabricated in different CMOS technologies (0.15μ, 0.13μ and 90 nanometer) for their sensitivity to radiationinduced single-event upsets. These results were compared to circuit simulation (Qcrit) studies, as well as to LANSCE neutron beam results and Crocker Nuclear Laboratory (U. C. Davis) cyclotron prot...

Due to aggressive technology scaling, radiation-induced soft errors have become a serious reliability concern in VLSI chip design. This paper presents a novel radiation hardened by design latch with high single-eventupset (SEU) immunity. The proposed latch can effectively mitigate SEU by internal dual interlocked scheme. The propagation delay, power dissipation and power delay product of the pr...

The methodology for the design and testing of fault tolerant systems implemented into an FPGA platform with different types of diagnostic techniques is presented in this paper. Basic principles of partial dynamic reconfiguration are described together with their impact on the fault tolerance features of the digital design implemented into the SRAM-based FPGA. The methodology includes detection ...

Xilinx® devices are designed to have an inherently low susceptibility to single event upsets (SEUs). This application note provides a substantial discussion of strategies and representative calculations for handling SEUs with an emphasis on reliability when addressing these low probability events. This application note introduces an SEU controller macro that can be included in any Virtex®-5 FPG...

Technology scaling relies on reduced nodal capacitances and lower voltages in order to improve performance and power consumption, resulting in significant increase in layout density, thus making these submicron technologies more susceptible to soft errors. Previous analysis indicates a significant improvement in SEU tolerance of the driver when the bias current is injected into the circuit but ...

Now a day's one of the most crucial issues in the field of FPGAGs, especially in SRAM FPGAs is single event upsets. One of the most effective methods to decrease these errors is using three dimensional FPGAs. This paper presents evaluation and mitigation of SEU cost on six layers three-dimensional (3D) FPGAs. The evaluation results show that SUE rate decrease about 67% on six layers 3D FPGAs. W...

Title of Dissertation: FUNCTIONAL ANALYSIS OF THREE ARABIDOPSIS TRANSCRIPTIONAL COREPRESSORS LINKING FLORAL REGULATORS TO ABA HORMONE SIGNALING Jayashree Sitaraman, Doctor of Philosophy, 2004 Dissertation Directed By: Associate Professor Zhongchi Liu Department Of Cell Biology and Molecular Genetics Hormonal signaling and developmental patterning have mostly been studied as separate and indepen...