In this paper, an ultra low power and low jitter 12bit CMOS digitally controlled oscillator (DCO) design is presented. Based on a ring oscillator implemented with low power Schmitt trigger based inverters. Simulation of the proposed DCO using 32nm CMOS Predictive Transistor Model (PTM) achieves controllable frequency range of 550MHz~830MHz with a wide linearity and high resolution. Monte Carlo ...

This paper proposes a high frequency ring oscillator with low power consumption. The proposed ring oscillator is based on Gated Ring Oscillator (GRO) by applying boot strap technique. Simulation results indicate that the FoM (Power Consumption /Oscillation Frequency) of the proposed ring oscillator is greater than that of the conventional ring oscillator. Figure 1 shows delay element using boot...

Clock recovery circuits are used in data communication systems for the system synchronization. In general a PLL (Phase Locked Loop) circuit is used to extract the clock signal from the input data stream. The recovered clock signal is always jittered and have to be adjusted by using a dejitter circuit. Tracking these errors over an extended period of time determines the system stability. Sources...

A CMOS LC-tank VCO and phase-shifting network are described for a direct-conversion receiver of IEEE 802.11a. The direct-conversion receiver is configured to have sub-harmonic mixing structure which requires multi-phase local oscillator (LO) signals spaced by 45°. A poly-phase filter with 3and 4-stage RC networks generates multi-phase LO signals whose amplitude imbalance is removed by cascaded ...

A completely monolithic high-Q oscillator, fabricated via a combined CMOS plus surface micromachining technology, is described, for which the oscillation frequency is controlled by a polysilicon micromechanical resonator with the intent of achieving high stability. The operation and performance of micromechanical resonators are modeled, with emphasis on circuit and noise modeling of multiport r...