This chapter presents the application of Differential Evolution (DE) Algorithm for the VLSI floorplanning problems. DE Algorithm has been successfully applied to VLSI sequence pair representation. The important advantages of DE are its simplicity, fast convergence, and easy for implementation. DE algorithm is a population based algorithm like GA using similar operators such as crossover, mutati...

The inter-wire spacing in a VLSI chip becomes closer as the VLSI fabrication technology rapidly evolves. Accordingly, it becomes important to minimize crosstalk caused by the coupling capacitance between adjacent wires in the layout design for the fast and safe VLSI circuits. We present a simulated annealing approach based on segment rearrangement to crosstalk minimization in an initially gridd...

In the VLSI industry, ability to anticipate variability tolerance is essential understanding circuits’ potential future performance. The cadence virtuoso tool used in this study assess how PVT fluctuations affect various fin-shaped field effect transistor (FinFET) circuits. research, high-performance FinFET-based circuits at 7 nm are discussed with a variation temperature and voltage. idea behi...

A major feature in computing history is the evolving ability to “write on silicon” and thereby create novel computational structures increasingly fast, compact power-efficient hardware. In 1978, Xerox PARC researcher MIT professor Lynn Conway, together with Caltech's Carver Mead, developed a simple powerful method of designing fabricating very large-scale integration (VLSI) integrated circuits....

The 41st IEEE VLSI Test Symposium (VTS) was held in San Diego, CA, USA, on 24–26 April 2023. This venue the first in-person one since COVID-19 pandemic. VTS is of premier conferences focusing test, reliability, and security challenges circuits. Following same trend as prior years, arranged three days captured a set research innovative practice (IP) sessions, keynotes, panels, embedded tutorials...

A parallel implementation of a genetic algorithm used to evolve simple analog VLSI circuits is described. The parallel computer system consisted of twenty distributed SPARC workstations whose computational activity is controlled by the parallel environment coordination language Linda. Work-in-progress on using the parallel GA to realize optimized circuits and to discover new types of equivalent...

Device mismatch in VLSI degrades the accuracy of analog arithmetic circuits and lowers the learning performance of large-scale neural networks implemented in this technology. We show compact, low-power on-chip calibration techniques that compensate for device mismatch. Our techniques enable large-scale analog VLSI neural networks with learning performance on the order of 10 bits. We demonstrate...

The hyperbolic tangent function and its derivative are key essential element in analog signal processing and especially in analog VLSI implementation of neuron of artificial neural networks. The main conditions of these types of circuits are the small silicon area, and the low power consumption. The objective of this paper is to study and design CMOS VLSI hyperbolic tangent function and its der...

With the advent of portable and high-density microelectronic devices, the power dissipation of very large scale integrated (VLSI) circuits is becoming a critical concern. Accurate and e cient power estimation during the design phase is required in order to meet the power speci cations without a costly redesign process. In this paper, we present a review/tutorial of the power estimation techniqu...

Simple to implement, low cost designs in CMOS Domino logic are presented. These designs require less transistors and are full Domino logic compatible while they attain better performance compared to the standard Domino logic implementations. Wide fan-in logic such as domino circuits is used in high-performance applications. Dynamic domino logic circuits are widely used in modern digital VLSI ci...