This paper describes the ideas and philosophy behind a new compact model (CM) for deep-submicron MOSFETs, called Xsim, which has been developed from scratch over the past few years. Similarities to and differences from existing popular models are pointed out. The opinions on many controversial debates in the CM field are given. The ultimate goal of the CM development in the context of technolog...

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The standard methods used for analysing the reliability of electronic systems are unsuited to VLSI systems because of their large-scale and software-driven nature. In this paper, a review of the problems is presented together with an analysis of the difficulties encountered in extrapolation of the present techniques. Some proposals are presented with the intention of making the solution more ma...

Innovation in infant disciplines occurs most rapidly and successfully when a large number of small groups proceed independently under the motivation of market opportunity. In a few years, a substantial fraction of the engineering work force will have a working knowledge of LSI design. At the same time, fabrication areas are becoming more and more capital intensive. What is needed is a clean, st...

A new fault tolerant multipipeline array architecture and its diagnosis/reconfiguration algorithm will be presented. This multipipeline array design methodology is characterized by constant, fault distribution independent interstage path lengths. Other features include a low hardware overhead and a high survival rate when it is compared to existing approaches.

General VLSI Cell placement has gone through different versions depending upon the particular applications. The area under modern challenges of VLSI desgin throw light on Power minimization, Thermal capacity and Area occupation. Thus Utility function, Renewal reward and Hypergraph setup are utilized in our discussion. A brief review is given in this paper . .

The catastrophic fault pattern is a pattern of faults occurring at strategic locations that may render a system unusable regardless of its component redundancy and of its reconfiguration capabilities. In this paper, we extend the characterization of catastrophic fault patterns known for linear arrays to two-dimensional VLSI arrays in which all links are unidirectional. We determine the minimum ...

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