This paper reports experiences and results gained during the evaluation of the visual formalism STD as speciication method for formal veriication, performed in cooperation with industrial partners. The visual formalism STD (Symbolic Timing Diagrams) was developed continuously since 1993 by OFFIS as a speciication method, which satisses several needs: (1) It is based on the principles used in th...

This paper describes work carried out to reduce the pessimism in distributed systems timing analysis. The starting point for the paper is the need to prove that the timing properties of a system are met in an efficient and effective manner. The paper shows that an exact approach to the analysis can be intractable, and other approaches are too pessimistic. Using extensive simulation, based on re...

We investigate the high-frequency timing jitter spectral density of mode-locked fiber lasers in different mode-locked regimes. Quantum-noise-limited timing jitter spectra of mode-locked-regime-switchable Yb fiber lasers are measured up to the Nyquist frequency with sub-100-as resolution. The integrated rms timing jitter of soliton, stretched-pulse, and self-similar Yb fiber lasers is measured t...

This paper presents an approach to cryptanalysis of RSA cryptosystem based on the application of genetic algorithm. The search utilizes the idea of timing attack as computation time information may leak due to different modular operations throughout the RSA encoding. This approach suggests a speed up process, aiming at reducing the required number of plaintext-ciphertext samples needed for a su...

Recent research has shown that implementations with variable execution timing may allow attackers to extract secret cryptographic keys stored on the device. Timing variances can occur due to implementation choices (e.g. data-dependent branches) or due to the internal architecture of the processor core (e.g. cache lines). In order to overcome this problem one needs to find alternative implementa...

Timing Analysis and Optimization Techniques for VLSI Circuits

To determine the quality of gate delay tests, Min/Max delay fault simulation must determine the detectable sizes of faults. In conventional Min/Max timing simulation, correlations at the inputs of reconvergent gates are ignored. This paper shows how correlation information can be used when fanouts reconverge to produce more accurate results.

The present paper is about French -ité nouns formation. More specifically, we are dealing with their interpretations. A deadjectival noun is a complex noun morphologically coined on an adjectival base. French deadjectival nouns formation (noted A > N) includes at least eight suffixes, as reported in Table 1. Actually, -ité is the most represented suffix in the biggest multivolume French diction...

This paper studies performance and timing failure probability of time-shifted redundant circuits and path-/circuit-replica circuits. Measurement-based experiments using a fabricated test chip are performed. For an approximately similar false positive error probability for the path-replica and circuit-replica, the false negative error probability of the circuit-replica is approximately two order...

A covert channel is a mechanism that can be used to communicate data across network or between processes within the system by violating the networks/ systems security policy and in a manner that goes unnoticed. An effective covert channel is the one that is undetectable by the adversary and can provide high degree of privacy. The goal of the covert channel is to communicate data from one host t...