Innovative synthesis for testability strategies aim at considering testability while synthesizing a circuit, whereas conventional design for testability methods modify the design after the circuit structure is synthesized. We describe a synthesis approach that maps a behavioral FSM description into a testable gate-level structure. The term “testable” in this context, besides implying the existe...

We study the query complexity of testing for properties defined by read once formulas, as instances of massively parametrized properties, and prove several testability and non-testability results. First we prove the testability of any property accepted by a Boolean read-once formula involving any bounded arity gates, with a number of queries exponential in , doubly exponential in the arity, and...

In property testing, we desire to distinguish between objects that have a given property and objects that are far from the property by examining only a small, randomly selected portion of the objects. Property testing arose in the study of formal verication, however much of the recent work has been focused on testing graph properties. In this thesis we introduce a generalization of property tes...

The demand for testing services is, to a large extend a “derived demand” influenced directly by the manner in which prior developed activities are undertaken. The early stages of a structured software development life cycle (SDLC) project can often run behind schedule, shrinking the time available for performing adequate testing especially when software release deadlines have to be met. This si...

We study the query complexity of testing for properties defined by read once formulas, as instances of massively parametrized properties, and prove several testability and non-testability results. First we prove the testability of any property accepted by a Boolean read-once formula involving any bounded arity gates, with a number of queries exponential in ǫ, doubly exponential in the arity, an...

C ryptographic circuits need special test infrastructure due to the concern of security involved. Normal design for testability methods, such as scan chains, as applied to most ASICs cannot be applied directly to Cryptographic chips. These methods, though providing the highest testability, open backdoors or side-channels for attackers, to extract secret keys or Intellectual Property information...

Local transformations are used in several synthesis approaches. During application of such transformations attention has to be paid to many important properties, e.g. area, speed, power consumption, and testability. In this paper we study relations between local transformations and delay fault testability. In delay testing it is not necessary to test every path in a circuit to ascertain correct...

Given software release deadlines, the early stages of a structured software development life cycle (SDLC) project can run behind schedule, shrinking the time allowed for performing adequate testing. This situation urges the need to start testing early and manage the testing effort efficiently. Our research examines how to assess the ways activities in the earlier stages of a project are progres...