An effective and scalable synchronization mechanism is necessary for a heterogeneous multiprocessor shared-memory system-on-a-chip (SoC). A system-on-a-chip lock cache (SoCLC) is a simple hardware unit that can easily be integrated to an SoC as an intellectual property (IP) core via the system bus and has been shown to achieve speedups of 55% and 27% in realistic examples at a very small (13,00...

The growing complexity of electronic systems has resulted in the development of large multiprocessor architectures. Many advanced consumer products such as mobile phones, PDAs and media players are based on System on Chip (SoC) solutions. These solutions consist of a highly integrated chip and associated software. SoCs combine hardware IP cores (function specific cores and accelerators) with on...

An all-digital on-chip delay measurement (OCDM) architecture with high delay measurement resolution and low supply voltage sensitivity for efficiently detection and diagnosis in the high performance system-on-chip (SoC) applications is presented. Based on the proposed differential delay line pair (DDLP) and an cascadestage delay line, the quantization resolution of the proposed OCDM not only ha...

This paper presents a new generic system architecture and design methodology for the design, debugging and testing of complex systems-on-chip (SoC). Starting from a hierarchical generic system architecture, platforms for dedicated application scenarios will be customized. In order to be able to handle very complex submicron designs, the system is based on a globally asynchronous and locally syn...

Peak detection is widely used in many signal-processing applications, since it allows automatic signal processing and produces faster result for users. In this work, an analysis of a peak detection algorithm implemented into a fieldprogrammable gate array (FPGA) is discussed. A system-on-chip (SoC) hardware architecture was designed using the Altera platform to analyse the system data flow. A s...

As system-on-chip (SoC) becomes prevalent in the intelligent system applications, the reliability issue of SoC is getting more attention in the design industry while the SoC fabrication enters the very deep submicron technology. The system bus, such as AMBA AHB, provides an integrated platform for IP-based SoC. Apparently, the robustness of system bus plays an important role in the SoC reliabil...

In modern computing, which relies on the interconnection of networks used in many/multi-core systems, any system can be critically subverted if is compromised. This done a multitude ways, but threat hardware Trojan (HT) being injected into particularly prevalent due to increase third-party manufacturers for system-on-chip (SoC) designs. With local injection an HT SoC, adversary gain access info...

Intelligent safety-critical systems, such as intelligent automotive systems or intelligent robots, require a stringent reliability while the systems are in operation. As system-on-chip (SoC) becomes prevalent in the intelligent system applications, the reliability issue of SoC is getting more attention in the design industry while the SoC fabrication enters the very deep submicron technology. T...

With the introduction of new generations of Systems on Chip (SoC) on 0.18 μm and 0.12μm technologies, the production cost and time to volume become more and more critical, on top of best in class level of quality and reliability. The SoC approach – widely based on the usage of cell libraries or reusable IP blocks – brings extreme complexity. Accurate knowledge and level of validation on silicon...

The Network-on-Chip (NoC) paradigm brings networks inside chips. We use the routing capabilities inside NoC to serve as a replacement for Virtual Method Table (VMT) for Object-Oriented (OO) designed hardware/software co-design systems where some methods could be implemented as hardware modules. This eliminates VMT area and performance overhead in OO co-designed embedded systems where resources ...