KEYWORDS analog circuit – fault diagnosis – test vector –tolerance –test node – multifrequency-modified nodal analysis ABSTRACT A method to identify and select test points for analog circuit testing and to detect multiple soft faults in linear analog circuits using multiple frequency measurements is proposed in this paper. Modified nodal analysis (MNA) method is used to simulate the circuit und...

This paper presents a low-cost analog test system with diagnosis capabilities. The tester is able to detect faults in any linear circuit by learning a reference circuit behavior in a first step, and comparing this behavior against the output of the circuit under test in a second step. For a faulty circuit, a third step takes place to locate the fault. The diagnosis method consists on injecting ...

Pseudo-exhaustive testing involves applying all possible input patterns to the individual output cones of a combinational circuit. Based on our new algebraic results, we have derived both generic (cone-independent) and circuit-specific (cone-dependent) bounds on minimal length of test required so that each cone in a circuit is exhaustively tested. For any circuit with five or fewer outputs, and...

In test mode test patterns are applied in random fashion to the circuit under circuit. This increases switching transition between the consecutive test patterns and thereby increases dynamic power dissipation. The proposed ring counter based ATPG reduces vertical switching transitions by inserting test vectors only between the less correlative test patterns. This paper presents the RC-ATPG with...

In this paper, we propose a test generation method for non-robust path delay faults using stuck-at fault test generation algorithms. In our method, we first transform an original combinational circuit into a circuit called a partial leaf-dag using path-leaf transformation. Then we generate test patterns using a stuck-at fault test generation algorithm for stuck-at faults in the partial leaf-dag...

The programming circuit of SRAM-based FPGAs consists of two shift registers, a control circuit and a configuration memory (SRAM) cell array. Because the configuration memory cell array can be easily tested by conventional test methods for RAMs, we focus on testing for the shift registers. We first derive test procedures for the shift registers, which can be done by using only the faculties of t...

This study describes a hardware modeling environment of built-in-self-test (BIST) for System on Chip (SOC) testing to ease the description, verification, simulation and hardware realization on Altera FLEX10K FPGA device. The very high speed hardware description language (VHDL) model defines a main block, which describe the BIST for SOC through a behavioral and structural description. The three ...

BACKGROUND Positive feedback is a common mechanism used in the regulation of many gene circuits as it can amplify the response to inducers and also generate binary outputs and hysteresis. In the context of electrical circuit design, positive feedback is often considered in the design of amplifiers. Similar approaches, therefore, may be used for the design of amplifiers in synthetic gene circuit...

The purpose of this paper is to present an efficient converter circuit used to drive switched reluctance motors. It uses the C-dump topology in which the trapped energy in the phase windings is returned to the supply capacitor to be used in the following strokes. In addition to the C-dump topology, it uses two extra feedbacks. One comes from a governor mounted on the shaft of motor which contro...