In some of the portable, power crucial and not-timing crucial applications more than 90% of the chip area will be occupied by memories and are powered by batteries. As in few applications batteries cannot be recharged it is very essential to reduce the power consumed by memory in order to increase the battery life time. Such application demand low power memories. In recent years a lot of work h...

This paper presents methods to reduce memory latency in the main memory subsystem below the board-level cache. We consider conventional page-mode DRAMs and cached DRAMs. Evaluation is performed via trace-driven simulation of a suite of nine benchmarks. In the case of page-mode DRAMs we show that it can be detrimental to use page-mode naively. We propose two enhancements that reduce overall memo...

— Aggressive CMOS scaling results in low threshold voltage and thin oxide thickness for transistors manufactured in deep submicron regime. As a result, reducing the subthreshold and tunneling gate leakage currents has become one of the most important criteria in the design of VLSI circuits. This paper presents a method based on dual-V t and dual-T ox assignment to reduce the total leakage power...

Back-end processors have been conventionally used for speeding up of only a specific set of compute intensive functions. Such co-processors are, generally, "hardwired" and cannot be used for a new function. In this paper, we discuss the design considerations and parameters of a general purpose reconfigurable co-processor. We also propose architecture of such a co-processor and discuss its imple...

The memory subsystem is a major contributor to the overall performance and energy consumption of embedded computing platforms. The emergence of "killer" applications such as data-intensive recognition, mining, and synthesis (RMS) applications puts even more stress on the memory subsystem and exacerbates its energy consumption. Traditional mechanisms to ensure data integrity deploy overdesign (e...

On chip memory or cache is an important piece of technology associated with lower energy consumption and increased system performance. The different configurations and technology types reveal many tradeoffs to be considered for optimizing a system designed for the consumer. The three main types of cache tech SRAM, STT-RAM, and eDRAM will be defined, and discussion will reveal what makes them go...

Several recent publications have shown that memory errors are common in high-performance computing systems, due to hardware faults in the memory subsystem. With exascale-class systems predicted to have 100-350x more DRAM and SRAM than current systems, these faults are predicted to become more common. Therefore, further study of the faults experienced by DRAM and SRAM is warranted. In this paper...

Spin-tronic memory is a promising technology and offers advantages due to its nonvolatility and higher density. At the same time, based on device properties, there are trade-offs that decide the energy and performance penalty overhead. To decide these trade-offs its it imperative to understand the sensitivity of different parameters in the memory subsystem. In this work, we use a known statisti...

Decoders are one of the significant peripheral components static random-access memory (SRAM). As CMOS technology moves towards nano scale regime, leakage power starts dominating dynamic power. In this paper, we propose decoders using NAND logic in 32 nm technology. Leakage is reduced by employing dual-threshold technique. Dual thresholding a technique that uses transistors two different thresho...