Full adder circuit is a basic building block for designing any arithmetic circuits. Due to high demands and need for low and high speed digital circuits with small silicon area scaling trends have increased tremendously. In this paper a new high speed full adder circuit is proposed with very less static and dynamic power dissipation which occupies less silicon area when compared with existing t...

We propose a hybrid power model for estimating the power dissipation of a design at the RT-level. This new model combines the advantages of both RT-level and gate-level approaches. We investigate the relationship between steadystate transition power and overall power dissipation. We observe that, statistically, two input sequences causing similar amount of steady-state transitions will exhibit ...

Gate oxide direct tunneling current is the major component of static power dissipation of a CMOS circuit for low-end technology, where the gate dielectric (SiO2) thickness is very low. This paper presents a novel direct tunneling current reduction method during behavioral synthesis of nanometer CMOS circuits. We provide analytical models to calculate the direct tunneling current and the propaga...

Power dissipation as a measure of peripheral resistance in vascular networks

SOFTWARE POWER ANALYSIS AND OPTIMIZATION FOR POWER-AWAREMULTICORE SYSTEMSbySHINANWANGMay 2014 Advisor: Dr. Weisong ShiMajor: Computer ScienceDegree: Doctor of Philosophy Among all the factors in sustainable computing, power dissipation and energy consump-tion, arguably speaking, are fundamental aspects of modern computer systems. Different fromperformance metric,...

| Decreasing capacitance of bus lines is one of the e ective ways to reduce whole power dissipation of LSIs. In this paper we compare microprocessors designed based on a bus architecture and a multiplexer architecture in terms of power dissipation and delay time. Through implementation of a test chip, the multiplexer architecture is e ective to reduce power dissipation by about 30%.

In this paper we focus on a novel generic method to decrease the power dissipation of the large number of output buffers (hundreds to thousands) that drive the large set of pixels, capacitor loads. By simply adding one or more appropriate surface mount inductors to the driver IC, RLC resonant circuits can be periodically constructed to charge and discharge the pixels. When the RLC resonant circ...

Perhaps reinforced by the notion of a Moore’s Law, technology scaling has provided the IC industry with an integration capacity of billions of transistors. As transistors keep shrinking in size, leakage power dissipation dramatically increases and gradually becomes a first-class design constraint in more and more designs. To provide higher performance at lower power and energy for micro-archite...

Motivation for reducing power dissipation during test application is presented. A scheme for reducing power dissipation during test application, when scan test structure is used, is proposed. Algorithms required to exploit the proposed technique are discussed. Experimental results are presented. keywords: Power dissipation, Full Isolated Scan, Full Integrated Scan.

This work provides a design for two types of sensors, based on the thermal dissipation and heat ratio methods of sap flow calculation, for moderate to large scale deployments for the purpose of monitoring tree transpiration. These designs include a procedure for making these sensors, a quality control method for the final products, and a complete list of components with vendors and pricing info...