A low-power 435-MHz single-ended low-noise amplifier was implemented in a 0.35-μm silicon on insulator (SOI) CMOS technology. The SOI CMOS LNA has a simulated noise figure of 0.6 dB, input 1-dB compression point of –12.5 dBm, input thirdorder intercept point of –5 dBm, and small-signal gain of 22 dB. Total power dissipation is 10 mW from a 2.5-V supply. LNA chip area is 1.4 mm x 0.58 mm. Due to...

Topological insulator (TI) states have been demonstrated in materials with a narrow gap and large spin-orbit interactions (SOI). Here we demonstrate that nanoscale engineering can also give rise to a TI state, even in conventional semiconductors with a sizable gap and small SOI. Based on advanced first-principles calculations combined with an effective low-energy k · p Hamiltonian, we show that...

We have analyzed the dominant noise sources in the driving circuit of an uncooled infrared radiation focal plane array fabricated on a silicon-on-insulator (SOI) substrate by 0.35 μm CMOS technology and bulkmicromachining. We found no noise property of SOI-MOSFET inferior compared to those of NMOSs formed on SOI and bulk substrate, respectively. In addition, we reduced the total noise of the se...

Thermal test structures and ring oscillators (ROs) are fabricated in 0.18-μm three-dimensional (3-D)–SOI technology. Measurements and electrothermal simulations show that thermal and parasitic effects due to 3-D packaging have a significant impact on circuit performance. A physical thermal model is parameterized to provide better prediction of circuit performance in 3-D technologies. Electrothe...

The El Niño – Southern Oscillation (ENSO) maintained its warm state through the austral spring of 2002, however the Southern Oscillation Index (SOI) remained only weakly negative, with values of –7.6, –7.4 and –6.0 for September, October and November respectively. This resulted in a seasonal mean SOI of –7.0, an increase of 1.5 since the winter season (Jones 2003). The SOI for spring (arguably)...

A cyclic A/D conversion circuit technique for sensor networks has been developed using 0.2-μm CMOS/FD-SOI technology. The FD-SOI analog switches can lower the supply voltage without degrading accuracy because of their negligible body effect. The proposed A/D converter achieves operation at the supply voltage of 1 V or less and can handle a sampling frequency ranging from 8 Sps to 8 kSps with a ...

We investigate thermal noise mechanisms and present analytical expressions of the noise power spectral density at high frequencies (HF) in Silicon-on-insulator (SOI) MOSFETs. The developed HF noise model of RF T-gate body contact (TB) SOI MOSFET for 0.13-μm SOI CMOS technology accounts for the mechanisms of 1) channel thermal noise; 2) induced gate noise; 3) substrate resistance noise and 4) ga...

This paper presents a new, simple method of measuring the generation lifetime in SOI (silicon-on-insulator) MOSFETS. Lifetime is extracted from the transient characteristics of MOSFET subthreshold current. Using this technique, generation lifetime was mapped across ®nished SIMOX (separation by implantated oxygen) wafers, BESOI (bonded and etchedback SOI) wafers, and UNIBOND wafers. BESOI materi...

We have developed a fully-depleted SOI-MOSFET model HiSIM-SOI for circuit simulation by solving the potential distribution along all three important SOI-surfaces selfconsistently. Besides comparison to measured I-V data, the model is verified with 1/f noise analysis, sensitive to the carrier concentration and distribution along the channel. The carrier concentration increase, due to confinement...

Gate tunneling current in fully depleted, double-gate (DG) silicon-on-insultor (SOI) MOSFETs is characterized based on quantummechanical principles. The gate tunneling current for symmetrical DG SOI with ground-plane ( =1.5 nm and =5 nm) is shown to be higher relative to single-gate (bulk) MOS structure. The tunneling is enhanced as the silicon layer becomes thinner since the thinner silicon la...