Complies with the regulations of this University and meets the accepted standards with respect to originality and quality. In order to meet the incessantly growing demand of performance, the amount of embedded or on-chip memory in microprocessors and systems-on-chip (SOC) is increasing. As much as 70% of the chip area is now dedicated to the embedded memory, which is primarily realized by the s...

An emerging technology known as Physical unclonable function (PUF) can provide a hardware root-of-trust in building the trusted computing system. PUF exploits intrinsic process variations during integrated circuit (IC) fabrication to generate unique response. This response differs from one other similar type of PUFs. Static random-access memory (SRAM-PUF) is memory-based PUFs which generated po...

SRAM is a most common embedded memory for CMOS ICs and it uses Bistable Latching circuitry to store a bit. This paper represents the simulation of different SRAM cells and their comparative analysis on different parameters such as Power Supply Voltage, Operating Frequency, Temperature and area efficiency etc. All the simulations have been carried out on BSIM 3V3 90nm technology at Tanner EDA tool.

A 90nm CMOS, 64Kbit, 1.16GHz, 16 port SRAM with multi-bank architecture realizing 590Gbps random access bandwidth, 41mW power dissipation at 1GHz and 0.91mm2 (13.9μm2/bit) area consumption is reported. Compared to conventional 16 port SRAM data, area and power consumption are reduced by factors 16 and 5, respectively, while maximum clock frequency is about a factor 2 higher.

SRAM bit fail maps (BFM) are routinely collected during earlier phases of yield ramping, providing a rich source of information for IC failure and deformation learning. In this paper, we present an automated approach to analyzing BFM data efficiently. We also demonstrate the usability of our analysis framework using real BFM test data from a large, modern SRAM test vehicle.

Single event upsets (SEU) produced by heavy ions in SOI CMOS SRAM cells were simulated using a mixed-mode approach, that is, two-dimensional semiconductor device simulation by TCAD tool coupled with circuit SPICE simulator. The effects of parasitic BJT and particle strike position on the SOI CMOS SRAM cells upset for transistor length scaling from 0.25 um to 65nm are presented.

This paper deals with design opportunities of Static Random Access Memory (SRAM) for low power consumption. Initially three major leakage current components are reviewed and then for a 6T SRAM cell, some of the leakage current reduction techniques are discussed. Finally double finger latch is analyzed and compared with single finger latch which shows reduction in sub threshold leakage current.

In this paper we are going to propose a new SRAM bitcell for the purpose of less power consumption, read stability,less area than the existing Schmitt trigger based SRAM and other existing designs through a new design which is combined of virtual grounding with Read error reduction logic. Designs and simulations were done using DSCH and Microwind.

Increased leakage current and device variability are posing major challenges to CMOS circuit designs in deeply scaled technologies. Static Random Accessed Memory (SRAM) has been and continues to be the largest component in embedded digital systems or Systems-onChip (SoCs). It is expected to occupy over 90% of the area of SoC by 2013 (Nakagome et al., 2003). As a result, SRAM is more vulnerable ...