A low–complexity direct digital frequency synthesizer based on linear interpolation method is presented in this paper. The proposed architecture employs a new technique to derive the slope coefficients at the first sample of each segment's interval thereby eliminating the ROM which stores those values. ROM elimination has resulted in significant logic element saving and simplified the whole DDF...

In this work one presented the design a 3bits, 10MSPS of a low power, high speed analog to digital pipelined Converter for CMOS image sensors. The OTA plays an important role in the ADC, because of its conversion rate and power consumption are limited by the performance of the OTA. The designed ADC in this paper employs parallel pipeline architecture based on Double Buffered S&H Circuit with CM...

In the interest of extending battery life in mobile systems that use pipelined ADCs, several power-efficient pipelined ADCs have recently been proposed. The most promising topologies reported thus far are those that substitute the opamp, which is the largest consumer of power in pipelined ADCs, with alternative and more power-efficient circuits. However, opamp-less pipelined ADCs thus far eithe...

Electrical Neurostimulation has been effective in several medical therapies and also for restoring physiological, sensory and neuromuscular deficits. The rectangular pulse waveform has been used as a standard shape for neural stimulation. However, it has been shown that non-rectangular waveforms provide a more energy-efficient neural stimulation. An ASIC has been developed composed of a stimula...

Introduction: Coherent phase modulated RF/photonic links have been proposed [1, 2] to realise high dynamic range analogue optical links, which require the use of an optical phase-locked loop (OPLL) as a linear phase demodulator. Through feedback, the OPLL forces the output phase response of a local optical phase modulator to mirror the phase of an incoming optical signal. Since high loop gain a...

An equation-based behavioral model has been developed to predict the real performance of a single–loop single-bit Sigma Delta Modulator (SDM). By using this prediction flow, not only can the circuit specifications be acquired, including the gain, bandwidth, slew rate of the OPAMPs, and the capacitor value in the switchedcapacitor circuits, but the real performance of the SDM can also be predict...

This work describes a 12-bit 100 MS/s 0.13 μm CMOS three-stage pipeline ADC with various circuit design techniques to reduce power and die area. Digitally controlled timing delay and gatebootstrapping circuits improve the linearity and sampling time mismatch of the SHA-free input network composed of an MDAC and a FLASH ADC. A single two-stage switched op-amp is shared between adjacent MDACs wit...

This paper proposes a 6b 1.2 GS/s 47.8 mW 0.17 mm 65 nm CMOS ADC for high-rate wireless personal area network systems. The proposed ADC employs a source follower-free flash architecture with a wide input range of 1.0 Vp-p at a 1.2 V supply voltage to minimize power consumption and high comparator offset effects in a nanometer CMOS technology. The track-and-hold circuits without source followers...

The present work deals with 12-bit Nyquist current-steering CMOS digital-to-analog converter (DAC) which is an essential part in baseband section of wireless transmitter circuits. Using oversampling ratio (OSR) for the proposed DAC leads to avoid use of an active analog reconstruction filter. The optimum segmentation (75%) has been used to get the best DNL and reduce glitch energy. This segment...