Precomputation is a recently proposed logic optimization technique which selectively disables the inputs of a logic circuit, thereby reducing switching activity and power dissipation, without changing logic functionality. In sequential precomputation, output values required in a particular clock cycle are selectively precomputed one clock cycle earlier, and the original logic circuit is “turned...

Present industrial applications require that logic synthesis should be scalable, which means that the algorithms used should have essentially linear complexity in circuit size. For this, we propose sequential rewriting and mapping with sequential choices. Sequential rewriting includes combinational rewriting and inherits its low computational complexity. During sequential rewriting, a history A...

Left-sequential logics provide a means for reasoning about (closed) propositional terms with atomic propositions that may have side effects and that are evaluated sequentially from left to right. Such propositional terms are commonly used in programming languages to direct the flow of a program. In this thesis we explore two such left-sequential logics. First we discuss Fully Evaluated Left-Seq...

Late changes in silicon design, called ECO, is a common although undesired practice. They happen due to last minute changes in the specifications or to design bugs found at the late stage, sometimes after the tapeout. At this stages going through the topdown design flow is infeasible, because it would take too long and lead to undesirably large perturbations to the physical layout. High-level d...

This paper proposes a technique for sequential logic equivalence checking by a structural fixed point iteration. Verification is performed by expanding the circuit into an iterative circuit array and by proving equivalence of each time frame by well-known combinational verification techniques. These exploit structural similarity between designs by local circuit transformations. Starting from th...

This paper deals with the test of an integrated on-line multiplier suitable for very large numbers. Due to the serial structure of the circuit, the controlability and observability of the different elements are very low. In particular, an embedded sequential Iterative Logic Array cannot be accessed directly and has no primary outputs. Thus some modifications of the circuit are made to enhance t...

Students studying undergraduate courses in digital electronics often lose interest in the subject, due to the short comings of learning tools that are commonly used to supplement such courses. Ideally learning tools increase student participation in the learning process and help in overcoming difficulties inherent to the subject. Comparisons have been drawn between the existing learning tools. ...

A fault simulator for large synchronous sequential circuits is presented in this paper. There are four key ideas to the fault simulator. 1) It uses the critical path tracing method to screen out the single event faults that need not map into equivalent stem faults. 2) It uses the single fault propagation method to map the traced single event faults into equivalent stem faults. 3) All the multip...

This paper describes the implementation of a featurebased visual tracking algorithm on a SIMD MasPar MP-1 and the mixed-mode PASM prototype. The sequential algorithm is introduced and a parallel version of the algorithm is described. Aspects of the mapping of this algorithm onto both machines are presented. Real image data was used to obtain timing results for all experiments. For the SIMD impl...

This module presents the basic structure of combinational logic circuits, and introduces the use of computer aided design (CAD) tools in modern circuit design. Combinational logic circuits use networks of logic gates to produce outputs that change in strict relation to input changes; that is, an output can only change state immediately after an input changes state. In a combinational circuit, s...