Software errors often occur at the interfaces between separately developed components. Incompatibilities are an especially acute problem when upgrading software components, as new versions may be accidentally incompatible with old ones. As an inexpensive mechanism to detect many such problems, previous work proposed a technique that adapts methods from formal verification to use component abstr...

Safety verification of while programs is often phrased in terms of inclusions L(A) ⊆ L(B) among regular languages. Antichainbased algorithms have been developed as an efficient method to check such inclusions. In this paper, we generalize the idea of antichain-based verification to verifying safety properties of recursive programs. To be precise, we give an antichain-based algorithm for checkin...

The demand for safety for electronic systems, especially safety critical systems, is high. Nowadays such systems are tested and simulated with a manually created set of test cases. But testing cannot reach a complete coverage for complex designs. Hence, we present a verification flow for Counting Heads for railways which are used by many electronic railway interlocking systems from SIEMENS. Our...

This report describes a formal approach to verification and validation of safety requirements for embedded software, by application to a simple control-logic case study. The logic is formally specified in Z. System safety properties are formalised by defining The paper develops a theoretical basis for assigning safety requirements for components of complex systems, including software, in a form...

In this paper we present a method for verifying Yhc bytecode, an intermediate form of Haskell suitable for mobile code applications. We examine the issues involved with verifying Yhc bytecode programs, and we present a proof-of-concept bytecode compiler and verifier. Verification is a static analysis which ensures that a bytecode program is type-safe. The ability to check type-safety is importa...

This paper identifies the software information that must be represented in a formal specification of source code level “safety verification conditions” (SVCs) for an object-oriented software system. The formalization does not necessarily require a notation with object-oriented constructs. In particular, a semantically simpler notation based on typed predicate logic is adequate for representing ...

Deep neural networks have achieved impressive experimental results in image classification, but can surprisingly be unstable with respect to adversarial perturbations, that is, minimal changes to the input image that cause the network to misclassify it. With potential applications including perception modules and end-to-end controllers for self-driving cars, this raises concerns about their saf...

Programmable Logic Controllers ensure the control of many reactive systems. These controllers are most of the time programmed with the languages defined in the IEC 61131– 3 standard. Our goal is the verification of safety properties of programs written in one of these languages: the Ladder Diagram. The main approaches in this field are based on ModelChecking. We propose in this article a Theore...

This paper investigates how formal techniques can be used for the analysis and verification of hybrid systems [1,5,7,16] — systems involving both discrete and continuous behavior. The motivation behind such research lies in the inherent similarity of the hierarchical and decentralized control strategies of hybrid systems and the communication and operation protocols used for distributed systems...

This paper describes ProMoVer, a tool for fully automated procedure–modular verification of Java programs equipped with method– local and global assertions that specify safety properties of sequences of method invocations. Modularity at the procedure–level is a natural instantiation of the modular verification paradigm, where correctness of global properties is relativized on the local properti...