In this paper a MMIC design technique, oriented to the optimization of the production yields, is illustrated together with the obtained results. This method, based on a sensitivity analysis, i.e. on the circuit behavior for variations of passive elements from their nominal value, and on the contemporary determination of the production yields, allows the identification the circuit elements to ob...

This paper presents a novel technique, which uses integer linear programming (ILP) to minimize the leakage power in a dual-threshold static CMOS circuit by optimally placing high-threshold devices and simultaneously reduces the glitch power using the smallest number of delay elements to balance path delays. The constraint set size for the ILP model is linear in the circuit size. Experimental re...

Inline with the advancement of low power circuit design, it has reduced the power requirements of electronic devices to the level of microwatts. As power demand decreases, the possibility of using energy harvesting systems as an alternative to batteries increases. However, for low power electronic application, the consistency of minimum voltage and current supply to the electronic devices is an...

Because of the growing complexity and the reduced turn-around time of modern designs, IP based strategies are becoming more and more popular. Usually, IPs are characterized as stand alone units, neglecting their mutual interaction. Unfortunately, this oversimplification is not always realistic. As a result, the overall operation of the circuit may be considerably affected. In fact, with the shr...

Synthetic biology is increasingly used to develop sophisticated living devices for basic and applied research. Many of these genetic devices are engineered using multi-copy plasmids, but as the field progresses from proof-of-principle demonstrations to practical applications, it is important to develop single-copy synthetic modules that minimize consumption of cellular resources and can be stab...

In this paper, the effect of number and fault current limiter(FCL) location has been investigated in order to have maximum reduction of short circuit current level in all buses in a real network. To do so, the faulty buses were identified in terms of short circuit current level by computing short circuits on the desired network. Then, while the fault current limit was modeled, its optimal locat...