Although domain-specialized FPGAs can offer significant area, speed and power improvements over conventional reconfigurable devices, there are several unique and unexplored design problems that complicate their development. One source of these problems is that designers often opt to replace more universal, fine-grain logic elements with a specialized set of coarse-grain functional units to impr...

Title of Thesis: AN O(1) DISTRISBUTED EXCEPTION HANDLING MECHANISM FOR DYNAMICALLY RECONFIGURABLE REAL-TIME SOFTWARE Degree Candidate: Jun Lang Degree and Year: Master of Science, Electrical Engineering, 1997 Thesis directed by: David B. Stewart, Assistant Professor Department of Electrical Engineering With programs growing in size and complexity, the quality and cost of developing and maintain...

In this work, we consider Reconfigurable Intelligent Meta-surfaces (RIMs) to provide effective beam steering functionality, while enhancing the coverage of fifth generation (5G) users in a urban city mobility context. particular, enable communications millimeter wave (mmWave) frequencies, that can occur simultaneously with other 5G communications. The main objective paper is demonstrate feasibi...

The paper deals with a new approach to the design of adaptive hardware using common Field Programmable Gate Arrays (FPGA). The ultimate aim is to develop evolvable IP (Intellectual Property) cores. The cores should be reused in the same way as ordinary IP cores are reused. In contrast to the conventional cores, the evolvable cores are able to perform autonomous evolution of their internal circu...

Recently researchers have shown interest in integrating Reconfigurable logic into conventional processors as a Reconfigurable Function Unit (RFU). A context-full RFU supports holding intermediate results inside itself, which eliminates some data movement overheads and has some other benefits. Most contemporary processors support out-of-order execution and speculation. When a context-full RFU is...

This paper describes the starting position for research beginning at the Department of Computing Science, University of Glasgow. The research will investigate a novel microprocessor design incorporating reconfigurable logic in its ALU, allowing the processor’s function units to be customised to suit the currently running application. We argue that this architecture will provide a performance ga...

Silicon technologies have been conforming to the maxim of Moore's law for the past 40 years [131], but, even though production prices per unit have gone down, the NRE costs for making new chips keep going up with every new technology. This made a number of applicationsectors discouraged to design new chips and in favour of adopting more generic solutions such as FPGAs and high-performance DSPs....

It has long been known that readers of this page will move their eyes from one fixation to the next two to four times per second. It follows from this fact that each fixation triggers a unique optic nerve volley lasting up to 300 ms that contains all the information the retina processes between fixations. Here we give such volleys a name (Retinal Functional Unit, RFU) and use human subjects and...

A complete hardware implementation of an evolvable combinational unit for FPGAs is presented. The proposed combinational unit consisting of a virtual reconfigurable circuit and evolutionary algorithm was described in VHDL independently of a target platform, i.e. as a soft IP core, and realized in the COMBO6 card. In many cases the unit is able to evolve (i.e. to design) the required function au...

In this paper we present the theoretical considerations and design evolution of a proof-of-concept reconfigurable metasurface, primarily used as tunable microwave absorber, but also wavefront manipulation polarization conversion device in reflection. We outline all taken into account, from selection patch shape, unit cell size, substrate, to topology structure that realizes desired tunability. ...