Recently, embedded reconfigurable computing has attracted great attention due to its potential to accelerate application execution. Its key feature is the ability to perform computations in hardware to increase performance, while retaining much of the flexibility of a software solution. Researchers in this field have reported substantial performance improvements for a variety of different appli...

This paper presents a reconfigurable architecture of a lab-on-chip (LoC) microarray device capable to process data either in genotyping or in gene expression applications in a fraction of the time that is required by the usual software methods running on a standard computer. The entire LoC consists of a microfluidics part for the sample preparation and hybridization, a microsystem part includin...

This paper presents the design alternatives for reconfigurable instruction set processors (RISP) from a hardware/software point of view. Reconfigurable instruction set processors are programmable processors that contain reconfigurable logic in one or more of its functional units. Hardware design of such a type of processors can be split in two main tasks: the design of the reconfigurable logic ...

Reconfigurable machines form a new class of machines that are designed around a specific part family of products and allow rapid change in their structure. They are designed to allow changes in machine configuration according to changes in production requirements. The reconfiguration may be related to changes in machine functionality or its scalability, i.e., the change in production volumes or...

We provide a methodology used for the temporal partitioning of the data-path part of an algorithm for a reconfigurable embedded system. Temporal partitioning of applications for reconfigurable computing systems is a very active research field and some methods and tools have already been proposed. But all these methodologies target the domain of existing reconfigurable accelerators or reconfigur...

The paper gives a brief survey over a decade of R&D on coarse grain reconfigurable hardware and related compilation techniques and points out its significance to the emerging discipline of reconfigurable computing.

High Performance Reconfigurable Computers exploit coarse and fine-grained parallelism through multiprocessors with reconfigurable logic devices. This paper addresses development and performance for defense-related applications such as hyperspectral imaging, simulation, and cryptography on HPRC platforms.

In the past few years, several satisfying various objectives and designs of reconfigurable integrated microwave filter and antenna have been proposed for wireless communication systems. Several designs are new concepts and techniques, whereas others are inspired from previous works. The improvement concepts of these designs can be reviewed from this compilation of studies. This paper begins wit...

Reconfigurable computing is a promising technology to meet future computational demand by leveraging flexibilities and the high degree of parallelism found in reconfigurable hardware fabrics, such as field programmable gate arrays (FPGAs) [1][2]. Reconfigurable computing had played an important role in the course of evolution of the computing paradigms. The journey of FPGAs had carried out from...

The aim of this work is the modeling and verification of concurrent systems that are subject to dynamic changes by using extensions of Petri nets. In previous studies, we have introduced net rewriting systems and a subclass of these called reconfigurable nets. In a net rewriting system, a system configuration is described as a Petri net and a change in configuration is described as a graph rewr...