The combination of feedback and quantization causes special problems. (Each on its own has its problems, like instability and round-off errors.) The main problem is the likely existence of multiple equilibria or limit cycles. Another is possible coherence between the input signal and quantization error or limit cycle, making the error indistinguishable from whatever signal characteristic we wan...

This paper presents two novel compensation circuits for leakage current and power supply noise (PSN) in phase locked loop (PLL) using a nanometer CMOS technology. The leakage compensation circuit reduces the leakage current of the charge pump circuit and the PSN compensation circuit decreases the effect of power supply variation on the output frequency of VCO. The PLL design is based on a 32nm ...

This paper presents two novel compensation circuits for leakage current and power supply noise (PSN) in phase locked loop (PLL) using nanometer CMOS technology. The leakage compensation circuit reduces the leakage current of the charge pump circuit which becomes more serious problem due to the thin gate oxide and small threshold voltage in nanometer CMOS technology and the PSN compensation circ...

A microprocessor clock generator based upon an analog phase-locked loop (PLL) is described for deskewing the internal logic control clock to an external system clock. This PLL is fully integrated onto a 1.2-million-transistor microprocessor in 0 . 8 p CMOS technology without the need for external components. It operates with a lock range from 5 up to 110 MHz. The clock skew is less than 0.1 ns,...

This paper focuses on the power grid oscillation of grid-side converter (GSC) in doubly-fed induction generator (DFIG) caused by sub-synchronous (SSO), and designs a measure to improve output quality GSC. Firstly, influence mechanism multipath disturbance GSC under SSO is sorted out, factors action modes are clarified. Secondly, estimation phase-locked loop (PLL) control strategy calculation pr...

In this paper, an adaptive sliding mode observer (ASMO) associated with a phase locked loop (PLL) is assessed for the sensor-less control of rotor-tied doubly-fed induction generator (RDFIG). proposed PLL-ASMO estimator, ASMO utilizes stator current, voltage, and back electromotive force (EMF) as state variables. The used in order to estimate back-EMF from which slip position/speed extracted us...

In this paper, a brief summary of synchronization approaches is discussed sequentially from older techniques to latest technology. There are many techniques that have been developed which focusing of synchronization, from basic grid evaluating technique, phase-locked-loop (PLL) and later to synchronous reference-frame phase-locked-loop where is established on basis of phase estimation and deter...

The aim of this study was to obtain accurate angular positions and velocities from resolver signals; resolver-to-digital conversion (RDC) often adopts a phase-locked loop (PLL) as demodulation algorithm. However, signals come with quadrature errors harmonics, which lead severe reduction in PLL accuracy. conventional does not consider the impact error, bandwidth is much larger than fundamental f...

In this article a novel charge pump circuit is introduced. The proposed circuit utilizes a bulk driven cascode current mirror through an adaptive gate bias technique, that results in a high output impedance over a very wide output voltage range, accurate Charge/ Discharge current matching, which minimizes the steady-state phase error in a phase-locked loop (PLL), and low transient glitches. The...

This paper presents a fully integrated 20-GHz frequency synthesizer based on an integer-N fourth-order type-II phase-locked loop (PLL). The PLL synthesizer employing a cross-coupled LC VCO was fabricated in a 0.13-μm SiGe:C BiCMOS process with a small chip area of 0.48 mm. The VCO core current is 4 mA. The full tuning range of the VCO is 2.21 GHz from 19.9 to 22.11 GHz, and the PLL can synthesi...