The problem of digit set conversion for xed radix is investigated for the case of converting into a non-redundant, as well as into a redundant digit set. Conversion may be from very general digit sets, and covers as special cases multiplier recodings, additions and certain multiplications. We generalize known algorithms for conversions into non-redundant digit sets, as well as apply conversion ...

This paper proposes a new fast method for calculating modular multiplication. The calculation is performed using a new representation of residue classes modulo M that enables the splitting of the multiplier into two parts. These two parts are then processed separately, in parallel, potentially doubling the calculation speed. The upper part and the lower part of the multiplier are processed usin...

Multiple Input Multiple Output Orthogonal Frequency Division Multiplexing technology is an advanced transmission technique for wireless communication systems. In this paper, the 64 point pipeline FFT/IFFT processor is introduced for efficient implementation of OFDM architecture. The IFFT processor is used to modulate the subcarrier in transmitter section and FFT processor demodulate the subcarr...

This paper presents an implementation of VLSI architecture for Dual Field Residue Arithmetic modular multiplier with less delay based on finite field arithmetic to support all public key cryptographic applications. A new method for incorporating Residue Number System (RNS) and Polynomial Residue Number system (PRNS) in modular multiplication is derived and then implemented VLSI Architecture for...

Bit-serial architectures have the advantage of high throughput, area efficient multipliers. These multipliers are implemented using shift-add operations [1], with full adders and D flip-flops as building blocks. Multiplication with a constant fixed-point coefficient is commonly used in digital signal processing (DSP) circuits, such as digital filters [2][3]. The design of a constant-coefficient...

In this paper we present the design of a new high-speed multiplication unit. The design is based on non-overlapped scanning of 3-bit ® elds of the multiplier. In this technique the partial products of the multiplicand and three bits of the multiplier are pre-calculated using only hardwired shifts. These partial products are then added using a tree of carry-save-adders, and ® nally the sum and c...

In this paper a new bit-parallel structure for a multiplier with low complexity in Galois elds is introduced. The multiplier operates over composite elds GF((2 n) m), with k = nm. The Karatsuba-Ofman algorithm is investigated and applied to the multiplication of polynomials over GF(2 n). It is shown that this operation has a complexity of order O(k log 2 3) under certain constraints regarding k...

Montgomery multiplication in GF(2) is defined by a(x)b(x) r−1(x) mod f(x), where the field is generated by irreducible polynomial f(x), a(x) and b(x) are two field elements in GF(2), and r(x) is a fixed field element in GF(2). In this paper, first we present a generalized Montgomery multiplication algorithm in GF(2). Then by choosing r(x) according to f(x), we show that efficient architecture f...

In this paper we present a VHDL code generator for a complex multiplier. The complex multiplier is based on a bit-parallel version of distributed arithmetic which reduces the hardware by nearly half compared to a straightforward implementation based on real multipliers. We choose an Overturned-Stairs adder tree to perform the summations in distributed arithmetic. The tree has a regular structur...

This project, along with the voltage multiplier chain with dual coil output to the boost converter provides a novel parallel input. On the one hand, and to take part in the input current and to reduce input curre nt ripple in the two coils in parallel with the primary windings connected. On the other hand, it is proposed to change, and a series of interleaved output capacitors profit profitable...