This paper presents the results of an architecture style evaluation that compares the performance of static scheduling and dynamic scheduling for media processors. Existing programmable media processors have predominantly used staticallyscheduled architectures. As future media processors progress to higher frequencies and higher degrees of parallelism, the dynamic aspects of processing become m...

This work explores the potential of sharing different arithmetic hardware operators tightly coupled to the integer pipeline of the open-source LEON3 processor. The idea is to map these modules to the same silicon area saving power consumption and area utilisation. The same strategy can be used to extend the architecture of processors optimized for applications with specific energy constraints. ...

An increasing cache latency in next-generation processors incurs profound performance impacts in spite of advanced out-of-order execution techniques. One way to circumvent this cache latency problem is to predict load values at the onset of pipeline execution by exploiting either the load value locality or the address correlation of stores and loads. In this paper, we describe a new load value ...

Finite structure query (fsq for short) is a tool for querying syntactically annotated corpora. fsq employs a query language of high expressive power, namely full first order logic. It can be used to query arbitrary finite structures, not just trees.

1383-7621/$ see front matter 2013 Elsevier B.V. A http://dx.doi.org/10.1016/j.sysarc.2013.04.002 q This is an extension of paper ‘‘Reducing L1 Caches Semantics’’, published in International Symposium o Design (ISLPED), July 30 – August 1, 2012. Compared material in this sumission mainly includes: optimiz detailed analysis on the counter-intuitive phenomen by kernel code; detailed analysis on ca...

Current microprocessors are designed to execute instructions in parallel and out of order. In general, superscalar processors fetch instructions in order. After the branch prediction logic determines whether a branch is taken (or not) and its target address, the processor decodes the instructions and renames the register operands, removing name dependences introduced by the compiler. Because pr...

for sorting n integers from the range !!.) algorithm p Optimal cost parallel algorithms for lexicographical ordering on a CREW PRAM are log n presented here. An 0 (I ( ) og nIp {I•...• n} usingp :::;; n processors is given here. Also an algorithm for sorting n strings of size lover an alphabet of size s is presented. that requires 0 ( log n[ ) .!!!.. + !.... ) units of time log (nllp p p and it...

Understanding the performance impact of compiler optimizations on superscalar processors is complicated because compiler optimizations interact with the microarchitecture in complex ways. This paper analyzes this interaction using interval analysis, an analytical processor model that allows for breaking total execution time into cycle components. By studying the impact of compiler optimizations...

In parallel computer systems with a number of processors, external fragmentation is caused by continuous allocation and deallocation of processors to tasks which require exclusive use of several contiguous processors. With this condition, the system may not be able to find contiguous processors to be allocated to an incoming task even with a sufficient number of free processors. Relocation is a...

Sequential pattern mining is the process of applying data mining techniques to a sequential database, to extract frequent subsequences to discover correlation that exists among the ordered list of events. Web Usage mining (WUM) discovers and extracts interesting knowledge/patterns from Web logs is one of the applications of Sequential Pattern Mining. In this paper, we present a survey of the se...